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[paper] Compact Schottky-barrier CNTFET Modeling

Manojkumar Annamalai and Michael Schroter

Compact formulation for the bias dependent quasi-static mobile charge in Schottky-barrier CNTFETs IEEE Transactions on Nanotechnology (2021)

DOI: 10.1109/TNANO.2021.3116694

CEDIC, Technische Universität Dresden (D)

Abstract: Carbon nanotube (CNT) field-effect transistors (FETs) are promising candidates for future high-frequency (HF) system-on-chip applications. Understanding and modeling mobile charge storage on CNTs is therefore essential for device optimization and circuit design. A physics-based compact analytical formulation is presented that enables an accurate approximation of the mobile charge in Schottky-barrier CNTFETs over the practically relevant bias range for HF circuit design. The formulation is C∞ continuous and yields accurate results also for the capacitances. The new formulation has been verified for both ballistic and scattering dominated carrier transport by employing device simulation, which was calibrated to experimental data from multi-tube CNTFETs.

Fig: Band diagram in a CNTFET along the axial direction (left red arrow) and, with applied gate bias, along the radial direction perpendicular to the gate (right blue arrow).

Acknowledgments: The authors would like to thank Dr. S. Mothes, formerly with CEDIC, for valuable discussions regarding the device simulator. This project was financially supported in part by the German National Science Foundation (DFG SCHR695/6-2).  

[paper] Gate Tunneling Current in MFIS NCFETs

Kshitiz Tyagi, Amit Verma, and Aloke K. Dutta

Modeling of the Gate Tunneling Current in MFIS NCFETs

IEEE Transactions on Electron Devices, pp. 1–8, Sept.18, 2021.

DOI: 10.1109/TED.2021.3114386

  

Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

  

Abstract: In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO2, and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance-a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Fig: Direct (DT) and Fowler–Nordheim (FN) tunneling modes of electrons having various energies, from the Si conduction band to the gate region

Acknowledgment: The authors would like to acknowledge the help of Mr. Amol Gaidhane at Nanolab, IIT Kanpur, in setting up the TCAD simulation workbench

[paper] Flexible Megahertz Organic Transistors

Jakob Leise^1,4, Jakob Pruefer^1,4, Ghader Darbandy¹, Aristeidis Nikolaou^1,4, Michele Giorgio², Mario Caironi², Ute Zschieschang³, Hagen Klauk³, Alexander Kloes¹, Benjamin Iñiguez⁴

and James W. Borchert⁵

Flexible megahertz organic transistors and the critical role of the device geometry on their dynamic performance

Journal of Applied Physics 130, 125501 (2021); 

DOI: 10.1063/5.0062146

  
1NanoP, TH Mittelhessen University of Applied Sciences, Gießen 35390, Germany
2Center for Nano Science and Technology @PoliMi, Istituto Italiano di Tecnologia, Milano 20133, Italy
3Max Planck Institute for Solid State Research, Stuttgart 70569, Germany
4DEEA, Uniersitat Rovira i Virgili, Tarragona 43007, Spain
5Georg August University of Goettingen, Goettingen 37077, Germany
  

Abstract: The development of organic thin-film transistors (TFTs) for high-frequency applications requires a detailed understanding of the intrinsic and extrinsic factors that influence their dynamic performance. This includes a wide range of properties, such as the device architecture, the contact resistance, parasitic capacitances, and intentional or unintentional asymmetries of the gate-to-contact overlaps. Here, we present a comprehensive analysis of the dynamic characteristics of the highest-performing flexible organic TFTs reported to date. For this purpose, we have developed the first compact model that provides a complete and accurate closed-form description of the frequency-dependent small-signal gain of organic field-effect transistors. The model properly accounts for all relevant secondary effects, such as the contact resistance, fringe capacitances, the subthreshold regime, charge traps, and non-quasistatic effects. We have analyzed the frequency behavior of low-voltage organic transistors fabricated in both coplanar and staggered device architectures on flexible plastic substrates. We show through S-parameter measurements that coplanar transistors yield more ideal small-signal characteristics with only a weak dependence on the overlap asymmetry. In contrast, the high-frequency behavior of staggered transistors suffers from a more pronounced dependence on the asymmetry. Using our advanced compact model, we elucidate the factors influencing the frequency-dependent small-signal gain and find that even though coplanar transistors have larger capacitances than staggered transistors, they benefit from substantially larger transconductances, which is the main reason for their superior dynamic performance.

Fig: Schematic cross-section of a top-contact (TC) organic TFT. Here, the semiconductor layer separates the source and drain contacts from the gate dielectric and thus from the gate-field-induced charge-carrier channel; hence, these transistors are also referred to as staggered TFTs. The overlap regions are assumed as a series connection of two capacitances. However, when the organic semiconductor (OSC) is operated in accumulation, the accumulation charges change the behavior of the series connection. The charge density at the source end of the channel is assumed to be found in the entire gate-to-source overlap region. 

Acknowledgments: The authors thankfully acknowledge funding for this project from the German Federal Ministry of Education and Research (“SOMOFLEX,” No. 13FH015IX6) and EU H2020 RISE (“DOMINO,” No. 645760), and the German Research Foundation (DFG) under Grant Nos. KL 1042/9-2, KL 2223/6-1, and KL 2223/6-2 (SPP FFlexCom). The authors would like

Memory for Synaptic Operations

Md. Hasan Raza Ansari, Udaya Mohanan Kannan and Seongjae Cho 

Core-Shell Dual-Gate Nanowire Charge-Trap Memory

for Synaptic Operations for Neuromorphic Applications

Nanomaterials 2021, 11, 1773

DOI 10.3390/nano11071773

 
Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea;
 

Abstract: This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Fig: Schematic representation of biological synapse and 2D representation of CSDG nanowire transistor for artificial synapse device.

Acknowledgement: This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (No. 2016M3A7B4910348, Nano-Material Technology Development Program, 50%) and was partly supported by Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-01294, Development of IoT based edge computing ultra-low power artificial intelligent processor, 50%).

[see also] M. H. R. Ansari, S. Cho, J.-H. Lee, and B.-G. Park, “Core-Shell Dual-Gate Nanowire Memory as a Synaptic Device for Neuromorphic Application,” IEEE Journal of the Electron Devices Society, pp. 1–1, 2021. DOI: 10.1109/JEDS.2021.3111343