[paper] CNTFET Technology for RF Applications

Martin Hartmann^1,2, Sascha Hermann^1,2,3, Phil F. Marsh⁴, Christopher Rutherglen⁴, 

Dawei Wang⁵, Li Ding⁶, Lian-Mao Peng⁶, Martin Claus⁷, 

and Michael Schröter⁷ (Senior Member, IEEE)

CNTFET Technology for RF Applications:

Review and Future Perspective

(Invited Paper)

IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, 2021

DOI: 10.1109/JMW.2020.3033781

¹Center for Microtechnology, Chemnitz University of Technology, Chemnitz, Germany
²Center for Advancing Electronics Dresden, Germany
³Fraunhofer Institute for Electronic Nanosystems, Chemnitz, Germany
⁴Carbonics Inc., Culver City, USA
⁵Carbon Technology Inc., Irvine, USA
⁶Key Laboratory for the Physics and Chemistry of Nanodevices 

and Center for Carbon-based Electronics,  Peking University, China
⁷Chair for Electron Devices and Integrated Circuits, Technical University Dresden, Germany

Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Fig: (a) sketch of a T-shape top gate on 4" wafer and (b) corresponding SEM image,

(c) SEM image in false colors depicting a multifinger buried gate CNTFET on an 8" wafer.

Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by the The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.

Von Neumann Is Struggling https://t.co/CQZ9RSnUNx #semi https://t.co/fbpB7K9TFw

Von Neumann Is Struggling https://t.co/CQZ9RSnUNx #semi pic.twitter.com/fbpB7K9TFw

— Wladek Grabinski (@wladek60) January 18, 2021

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from Twitter https://twitter.com/wladek60

January 18, 2021 at 09:47AM
via IFTTT

Virtual Si Museum /2103/ Electron Devices Scaling

Other look at the electron device scaling: Trinitron CRT vs iPhone6 Retina HD LED display. Both were extracted for broken units:) Trinitron CRT (Sony's brand name for its line of aperture-grille-based CRTs) were introduced in 1968. Its standard TV resolution was 720x576-pixel for PAL. iPhone6 available since 2014 has the HD LED display 1334x750-pixel. Just estimate volume, resolution and power consumption scaling in both cases.

REF:

• Sony Trinitron A13JZVOOX
  5-inch (diagonal) CRT 720x576-pixel resolution for PAL at 192 ppi
• iPhone6 Retina HD display
  4.7-inch (diagonal) LED 1334x750-pixel resolution at 326 ppi

[paper] MEMS thermal actuators

Longchang Ni, Ryan M. Pocratsky and Maarten P. de Boer 

Demonstration of tantalum as a structural material for MEMS thermal actuators 

Microsyst Nanoeng 7, 6 (2021) 

DOI: 10.1038/s41378-020-00232-z 

CMU Mechanical Engineering Dept., Pittsburgh, PA, USA

Abstract: This work demonstrates the processing, modeling, and characterization of nanocrystalline refractory metal tantalum (Ta) as a new structural material for microelectromechanical system (MEMS) thermal actuators (TAs). Nanocrystalline Ta films have a coefficient of thermal expansion (CTE) and Young’s modulus comparable to bulk Ta but an approximately ten times greater yield strength. The mechanical properties and grain size remain stable after annealing at temperatures as high as 1000 °C. Ta has a high melting temperature (Tm = 3017 °C) and a low resistivity (ρ = 20 µΩ cm). Compared to TAs made from the dominant MEMS material, polycrystalline silicon (polysilicon, Tm = 1414 °C, ρ = 2000 µΩ cm), Ta TAs theoretically require less than half the power input for the same force and displacement, and their temperature change is half that of polysilicon. Ta TAs operate at a voltage 16 times lower than that of other TAs, making them compatible with complementary metal oxide semiconductors (CMOS). We select α-phase Ta and etch 2.5-μm-thick sputter-deposited films with a 1 μm width while maintaining a vertical sidewall profile to ensure in-plane movement of TA legs. This is 25 times thicker than the thickest reactive-ion-etched α-Ta reported in the technical literature. Residual stress sensitivities to sputter parameters and to hydrogen incorporation are investigated and controlled. Subsequently, a V-shaped TA is fabricated and tested in air. Both conventional actuation by Joule heating and passive self-actuation are as predicted by models.

Fig: Top view of freestanding Ta thermal actuator. In-plane deflection δ ≈ 5µm after hydrogen degas step

Acknowledgements: This work was partially supported by the US National Science Foundation (NSF) grant number CMMI-1635332. We also acknowledge the Kavcic-Moura Endowment Fund for the support. We would like to thank the executive manager, Matthew Moneck, and all the staff members of the CMU Eden Hall Foundation Cleanroom for their guidance and advice on equipment usage and process development. We also acknowledge the use of the Materials Characterization Facility at Carnegie Mellon University under grant # MCF-677785

[paper] Subtractive photonics

Reza Fatemi, Craig Ives, Aroutin Khachaturian, and Ali Hajimiri

Subtractive photonics

Optics Express Vol. 29, Issue 2, pp. 877-893 (2021)

DIO: 10.1364/OE.410139

California Institute of Technology, 1200 E. California Blvd., Pasadena, CA 91125, USA

Abstract: Realization of a multilayer photonic process, as well as co-integration of a large number of photonic and electronic components on a single substrate, presents many advantages over conventional solutions and opens a pathway for various novel architectures and applications. Despite the many potential advantages, realization of a complex multilayer photonic process compatible with low-cost CMOS platforms remains challenging. In this paper, a photonic platform is investigated that uses subtractively manufactured structures to fabricate such systems. These structures are created solely using simple post-processing methods, with no modification to the foundry process. This method uses the well-controlled metal layers of advanced integrated electronics as sacrificial layers to define dielectric shapes as optical components. Metal patterns are removed using an etching process, leaving behind a complex multilayer photonic system, while keeping the electronics'metal wiring intact. This approach can be applied to any integrated chip with well-defined metallization, including those produced in pure electronics processes, pure photonics processes, heterogeneously integrated processes, monolithic electronic-photonic processes, etc. This paper provides a proof-of-concept example of monolithic electronic-photonic integration in a 65 nm bulk CMOS process and demonstrates proof-of-concept photonic structures. The fabrication results, characterization, and measurement data are presented.

Fig: The fabricated chip with various photonic structures in a measurement setup.