Virtual Si Museum /2103/ Electron Devices Scaling

Other look at the electron device scaling: Trinitron CRT vs iPhone6 Retina HD LED display. Both were extracted for broken units:) Trinitron CRT (Sony's brand name for its line of aperture-grille-based CRTs) were introduced in 1968. Its standard TV resolution was 720x576-pixel for PAL. iPhone6 available since 2014 has the HD LED display 1334x750-pixel. Just estimate volume, resolution and power consumption scaling in both cases.

REF:

• Sony Trinitron A13JZVOOX
  5-inch (diagonal) CRT 720x576-pixel resolution for PAL at 192 ppi
• iPhone6 Retina HD display
  4.7-inch (diagonal) LED 1334x750-pixel resolution at 326 ppi

[paper] MEMS thermal actuators

Longchang Ni, Ryan M. Pocratsky and Maarten P. de Boer 

Demonstration of tantalum as a structural material for MEMS thermal actuators 

Microsyst Nanoeng 7, 6 (2021) 

DOI: 10.1038/s41378-020-00232-z 

CMU Mechanical Engineering Dept., Pittsburgh, PA, USA

Abstract: This work demonstrates the processing, modeling, and characterization of nanocrystalline refractory metal tantalum (Ta) as a new structural material for microelectromechanical system (MEMS) thermal actuators (TAs). Nanocrystalline Ta films have a coefficient of thermal expansion (CTE) and Young’s modulus comparable to bulk Ta but an approximately ten times greater yield strength. The mechanical properties and grain size remain stable after annealing at temperatures as high as 1000 °C. Ta has a high melting temperature (Tm = 3017 °C) and a low resistivity (ρ = 20 µΩ cm). Compared to TAs made from the dominant MEMS material, polycrystalline silicon (polysilicon, Tm = 1414 °C, ρ = 2000 µΩ cm), Ta TAs theoretically require less than half the power input for the same force and displacement, and their temperature change is half that of polysilicon. Ta TAs operate at a voltage 16 times lower than that of other TAs, making them compatible with complementary metal oxide semiconductors (CMOS). We select α-phase Ta and etch 2.5-μm-thick sputter-deposited films with a 1 μm width while maintaining a vertical sidewall profile to ensure in-plane movement of TA legs. This is 25 times thicker than the thickest reactive-ion-etched α-Ta reported in the technical literature. Residual stress sensitivities to sputter parameters and to hydrogen incorporation are investigated and controlled. Subsequently, a V-shaped TA is fabricated and tested in air. Both conventional actuation by Joule heating and passive self-actuation are as predicted by models.

Fig: Top view of freestanding Ta thermal actuator. In-plane deflection δ ≈ 5µm after hydrogen degas step

Acknowledgements: This work was partially supported by the US National Science Foundation (NSF) grant number CMMI-1635332. We also acknowledge the Kavcic-Moura Endowment Fund for the support. We would like to thank the executive manager, Matthew Moneck, and all the staff members of the CMU Eden Hall Foundation Cleanroom for their guidance and advice on equipment usage and process development. We also acknowledge the use of the Materials Characterization Facility at Carnegie Mellon University under grant # MCF-677785

[paper] Subtractive photonics

Reza Fatemi, Craig Ives, Aroutin Khachaturian, and Ali Hajimiri

Subtractive photonics

Optics Express Vol. 29, Issue 2, pp. 877-893 (2021)

DIO: 10.1364/OE.410139

California Institute of Technology, 1200 E. California Blvd., Pasadena, CA 91125, USA

Abstract: Realization of a multilayer photonic process, as well as co-integration of a large number of photonic and electronic components on a single substrate, presents many advantages over conventional solutions and opens a pathway for various novel architectures and applications. Despite the many potential advantages, realization of a complex multilayer photonic process compatible with low-cost CMOS platforms remains challenging. In this paper, a photonic platform is investigated that uses subtractively manufactured structures to fabricate such systems. These structures are created solely using simple post-processing methods, with no modification to the foundry process. This method uses the well-controlled metal layers of advanced integrated electronics as sacrificial layers to define dielectric shapes as optical components. Metal patterns are removed using an etching process, leaving behind a complex multilayer photonic system, while keeping the electronics'metal wiring intact. This approach can be applied to any integrated chip with well-defined metallization, including those produced in pure electronics processes, pure photonics processes, heterogeneously integrated processes, monolithic electronic-photonic processes, etc. This paper provides a proof-of-concept example of monolithic electronic-photonic integration in a 65 nm bulk CMOS process and demonstrates proof-of-concept photonic structures. The fabrication results, characterization, and measurement data are presented.

Fig: The fabricated chip with various photonic structures in a measurement setup.

[paper] Fabrication EM AlGaN/GaN MIS HEMT

Flavien Cozette¹, Bilal Hassan¹, Christophe Rodriguez¹, Eric Frayssinet², Rémi Comyn², François Lecourt³, Nicolas Defrance⁴, Nathalie Labat⁵, François Boone¹, Ali Soltani¹, Abdelatif Jaouad¹, Yvon Cordier² and Hassan Maher¹

New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

2021 Semicond. Sci. Technol. 36 034002

DOI: 10.1088/1361-6641/abd489

¹LN2, CNRS-UMI-3463, 3IT, Université de Sherbrooke, Canada

²Université Côte d'Azur, CNRS, CRHEA, Valbonne, France

³OMMIC, 94450 Limeil-Brévannes, France

⁴IEMN, CNRS-UMR-8520, University of Lille, France

⁵IMS, CNRS-UMR-5218, University of Bordeaux, France

Abstract: This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (Vth) of +0.4 V and +0.9 V respectively with ΔVth about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an ION/IOFF about 108 and a breakdown voltage of VBR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.

Fig: SEM image of an E-mode device.

Acknowledgments: This work was supported by Fonds de Recherches du Québec—Nature, Technologies (FRQNT), the Natural Sciences and Engineering Research Council of Canada (NSERC), French technology facility network RENATECH and the French National Research Agency (ANR) through the projects ED-GaN (ANR-16-CE24-0026-02) and the 'Investissements d'Avenir' program GaNeX (ANR-11-LABX-0014).

Imec’s Plan For Continued Scaling: “Towards Atomic Channels and Deconstructed Chips” https://t.co/rUAJ5qPJOO #semi https://t.co/CiRNgqPsHG

Imec’s Plan For Continued Scaling: “Towards Atomic Channels and Deconstructed Chips” https://t.co/rUAJ5qPJOO #semi 

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