[EMPHASIS] Virtual Launch Event

Virtual Launch Event 

of EMPHASIS Research Centre

University of Cyprus

In case you missed any parts of the event, the recording can be found at the link below on our YouTube channel:

https://www.youtube.com/watch?v=Rc0ALhwGU6M&ab_channel=EmphasisResearchCentre

For more information, please reach out 

info.emphasis@ucy.ac.cy or 

iezekiel@ucy.ac.cy  EMPHASIS Director 

Sincerely,

Chrysafis Andreou, PhD

Lecturer

Department of Electrical and Computer Engineering

Emphasis Research Centre

University of Cyprus

[FOSDEM 2021] Open Source Computer Aided Design and Modeling devroom

We are pleased to announce the CfP for: 

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Open Source Computer Aided Design and Modeling devroom 

at FOSDEM 2021, 

on Sunday, 7 February 2021 

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FOSDEM website:

https://fosdem.org/2021/

FOSDEM Code of Conduct:

https://fosdem.org/2021/practical/conduct/

We hope you'll join us for a full day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. This year's event will be fully virtual and will feature multiple channels for talks, Q&A as well as hallway discussions.

We welcome any talk proposals about the creation of physical objects.

Topics of interest include, but are not limited to:

- Open Hardware projects

- Circuit Design
    * Printed circuit board design tools
    * Circuit simulation
- 3d modeling and analysis
    * Solid modeling tools
    * Meshing, modeling and transforming physical representations
    * Finite element analysis
- 3d printing
    * 3d slicing tools
    * Motor control
- Machine design and integration
    * ECAD/MCAD integration
    * Thermal analysis
    * Wire modeling
- Physical Model Data storage
    * Data representation and optimization
    * Version control in hardware data storage
    * Collaborative and team-based hardware design techniques

Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.

The submission process

Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM21

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.

Please include the following information with your submission:

- Abstract

- Preferred Session length

- Speaker bio

- Link to any hardware / code /slides for the talk

When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Open Source Computer Aided Modeling and Design" in the track drop-down menu. Otherwise, your proposal may go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers.

Important dates

- Call for papers available: 2 December 2020
- Call for participation closes: 20 December 2020
- Devroom schedule available: 24 December 2020
- Talk recording uploads due: no later then 14 January 2020
- Devroom day: Sunday 7 February 2021 (09:00 to 17:00)

Recordings
Because this year's conference will be fully virtual, all talks must be pre-recorded.  These will be verified for sound and video quality prior to the conference.

Each accepted talk will have a dedicated chaperone to help you through the process of recording, encoding and uploading your talk.

The recordings will be published under the same license as all FOSDEM
content (CC-BY).

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open-hardware-devroom mailing list
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom

IEEE EDS Golden List of Reviewers

Golden List of Reviewers for 2020

IEEE TED, Vol. 67, No. 12, Dec. 2020

Stat Data

Country	Reviewers
USA	559
China	286
India	159
Japan	151
S.Korea	121
Taiwan	111
Italy	102
Germany	90
United Kingdom	79
France	64
Belgium	63
Singapore	35
Switzerland	29
Austria	28
Spain	27
Hong Kong	25
Russia	22
Canada	22
Netherlands	19
Iran	14
Brazil	14
Turkey	12
Australia	12
Sweden	10
Poland	10
Greece	10
Saudi Arabia	8
Mexico	8
Israel	5
Ukraine	4
Slovakia	3
Portugal	3
Malaysia	3
Kazakhstan	3
Egypt	3
Algeria	2
Bulgaria	2
Denmark	2
Finland	2
Latvia	2
Lithuania	2
Qatar	2
Romania	2
Venezuela	2
Bangladesh	1
Belarus	1
Croatia	1
Czechia	1
Ireland	1
Kuwait	1
Lebanon	1
Macedonia	1
Slovenia	1
Tunisia	1
UAE	1

[paper] THz characterization and modeling of SiGe HBTs

Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE

THz characterization and modeling of SiGe HBTs

review (invited)

IEEE J-EDS, 2020, pp.1-1 

DOI:10.1109/JEDS.2020.3036135

hal-03014869

IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)

Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.

Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.

A complete description of probe topology and technology is given in:

A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241

Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.

[paper] SPICE-level Crossbar-array Circuit Simulator

Fan Zhang¹ and Miao Hu² 

CCCS: Customized SPICE-level Crossbar-array Circuit Simulator

for In-Memory Computing

IEEE/ACM International Conference on Computer-Aided Design

(ICCAD ’20) November 2– 5, 2020, Virtual Event, USA. 

ACM, New York, NY, USA, 8 pages.

DOI: 10.1145/3400302.3415627

1Arizona State University Tempe, Arizona
2Binghamton University Binghamton, New York

ABSTRACT: Resistive crossbar arrays are known for their unique structure to implement analog in-memory vector-matrix-multiplications (VMM). However, general-purpose circuit simulators, such as HSPICE and HSIM, are too slow for large scale crossbar array simulations with consideration of circuit parasitics. Although there are some specific simulators designed for crossbar arrays, they mainly focus on area/power/delay estimation rather than accurate SPICE-level simulation, thus could not model its functionality on analog in-memory computing. In this paper, we firstly give a SPICE-level modeling of resistive crossbar array with consideration of circuit parasitics in MATLAB. We also propose efficient methods to further speedup simulations by model simplifications. Last but not least, ResNet-20 on CIFAR-10 is applied to demonstrate the work. With the proposed model simplification methods, simulation speed can be improved by ~31X with tolerable errors, and more than 5X speedup is achieved on ResNet-20 while the accuracy drop is 6%.

Figure: Implement the ResNet on the crossbar with sub-block optimization. 

RELATED WORK: Other than general-purpose circuit simulators, specific simulation platforms have been proposed for crossbar-based application analysis; examples include: 

[MNSIM] L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. MNSIM: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 469–474.
[NeuroSim] P. Chen, X. Peng, and S. Yu. 2018. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 12 (Dec 2018), 3067–3080.