Golden List of Reviewers for 2020
Dec 2, 2020
Dec 1, 2020
[paper] THz characterization and modeling of SiGe HBTs
Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE
THz characterization and modeling of SiGe HBTs
review (invited)
IEEE J-EDS, 2020, pp.1-1
DOI:10.1109/JEDS.2020.3036135
hal-03014869
IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)
Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.
Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.
A complete description of probe topology and technology is given in:
A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241
Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.
Nov 30, 2020
[paper] SPICE-level Crossbar-array Circuit Simulator
Fan Zhang1 and Miao Hu2
CCCS: Customized SPICE-level Crossbar-array Circuit Simulator
for In-Memory Computing
IEEE/ACM International Conference on Computer-Aided Design
(ICCAD ’20) November 2– 5, 2020, Virtual Event, USA.
ACM, New York, NY, USA, 8 pages.
DOI: 10.1145/3400302.3415627
1Arizona State University Tempe, Arizona2Binghamton University Binghamton, New York
ABSTRACT: Resistive crossbar arrays are known for their unique structure to implement analog in-memory vector-matrix-multiplications (VMM). However, general-purpose circuit simulators, such as HSPICE and HSIM, are too slow for large scale crossbar array simulations with consideration of circuit parasitics. Although there are some specific simulators designed for crossbar arrays, they mainly focus on area/power/delay estimation rather than accurate SPICE-level simulation, thus could not model its functionality on analog in-memory computing. In this paper, we firstly give a SPICE-level modeling of resistive crossbar array with consideration of circuit parasitics in MATLAB. We also propose efficient methods to further speedup simulations by model simplifications. Last but not least, ResNet-20 on CIFAR-10 is applied to demonstrate the work. With the proposed model simplification methods, simulation speed can be improved by ~31X with tolerable errors, and more than 5X speedup is achieved on ResNet-20 while the accuracy drop is 6%.
Figure: Implement the ResNet on the crossbar with sub-block optimization.
RELATED WORK: Other than general-purpose circuit simulators, specific simulation platforms have been proposed for crossbar-based application analysis; examples include:
[MNSIM] L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. MNSIM: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 469–474.
[NeuroSim] P. Chen, X. Peng, and S. Yu. 2018. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 12 (Dec 2018), 3067–3080.
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[paper] The advantages of p-GaN channel/Al2O3 gate insulator
Maria Ruzzarin,1, Carlo De Santi,1 Feng Yu,2 Muhammad Fahlesa Fatahilah,2 Klaas Strempel,2 Hutomo Suryo Wasisto,2 Andreas Waag,2 Gaudenzio Meneghesso,1 Enrico Zanoni,1
and Matteo Meneghini1
Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator
Appl. Phys. Lett. 117, 203501 (2020);
DOI: 10.1063/5.0027922
Published Online: 16 November 2020
1 Department of Information Engineering, University of Padova, via Gradenigo 6/b, 35131 Padova, Italy
2 Institute of Semiconductor Technology (IHT) and Laboratory for Emerging Nanometrology (LENA), Technische Universitat Braunschweig, Langer Kamp 6a/b, 38106 Braunschweig, Germany
Abstract: We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.
Fig. a) The p-channel device (Gen2) comprises a 2.5 lm n-GaN buffer layer, a 0.5 lm p-GaN channel layer, 0.73 lm n-GaN and 0.5 lm n p-GaN as the top layer, and 25 nm-Al2O3 as the gate dielectric.
b) SEM images of a nanowire of the p-channel device (Gen2) and bird’s-eye view of vertically aligned n-p-n GaN nanowire (NW) arrays with top contacts.
Aknowledgement: This work was supported in part by NoveGaN (Univ. of Padova) through the STARS CoG Grants call. Ack prog. Eccellenza. This research was partly performed within project INTERNET OF THINGS: SVILUPPI METODOLOGICI, TECNOLOGICI E APPLICATIVI and co-funded (2018–2022) by the Italian Ministry of Education, Universities and Research (MIUR) under the aegis of the “Fondo per il finanziamento dei dipartimenti universitari di eccellenza” initiative (Law 232/2016). Financial support from the German Research Foundation (DFG) of 3D GaN project and the Lower Saxony Ministry of Science and Culture (N-MWK) of LENA-OptoSense group is highly acknowledged for the development of vertical GaN nanowire FETs.
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