[paper] Parameter Extraction in JFETs

Nikolaos Makris¹, Matthias Bucher¹, Member, IEEE, Loukas Chevas¹, Farzan Jazaeri²

and Jean-Michel Sallese²

Free Carrier Mobility, Series Resistance, and Threshold Voltage Extraction
in Junction FETs

in IEEE Transactions on Electron Devices, 

Special Section on ESSDERC/ESSCIRC 2020

DOI: 10.1109/TED.2020.3025841.

¹School of Electrical and Computer Engineering, TU Crete (GR)

²Ecole Polytechnique Fédérale de Lausanne, EPFL (CH)

Abstract: In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself may be determined from the measurement from two FETs with different channel lengths. The key technological and design parameter is the threshold voltage, which may be unambiguously determined from the transconductance-to-current ratio with a constant-current method. The new methods are shown to be effective over a wide range of technical parameters, using technology computer-aided design simulations.

Fig: Extraction of carrier mobility for DG JFETs in linear region at 300K 

a) corresponding output conductance gds and constituents ∂gds/∂Vds and 2Qsc,d/b, and 

b) extracted mobility for long- and moderate-length devices close agreement with the constant, nonfield-dependent mobility (μ = 826 cm2/Vs) used in the TCAD simulations.

Aknowlegement: This work was supported in part by the INNOVATION-EL-Crete Project under Grant MIS 5002772. 

[paper] Compact Modeling in MFIS Negative-Capacitance FETs

N. Pandey and Y. S. Chauhan

Analytical Modeling of Short-Channel Effects in MFIS Negative-Capacitance FET

Including Quantum Confinement Effects

in IEEE TED (Early Access), DOI: 10.1109/TED.2020.3022002.

Abstract: An analytical 2-D model of double-gate metal-ferroelectric-insulator-semiconductor-negative-capacitance FET (MFIS-NCFET), using Green's function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau-Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from potential functions. The developed model includes quantum-mechanical effects, which considers not only geometrical confinements but also electrical confinements. The analytical solution of a 2-D nonhomogeneous Poisson equation coupled with the 1-D Schrödinger equation is used to obtain the potential function in the channel. The impact of the ferroelectric thickness (tfe) on quantum confinement is also studied. We find that larger tfe reduces the quantum confinement effect. Therefore, as tfe increases, threshold voltage roll-off with the variation in Si-body thickness decreases.

Fig: Schematic of DG MFIS-NCFET.

Aknowegement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA-02/2017-18 and in part by the FIST Scheme of the Department of Science and Tech- nology under Grant SR/FST/ETII-072/2016. 

[paper] gm/ID-Based Sizing for Analog ICs

Tuotian Liao and Lihong Zhang

An LDE-Aware gm/ID-Based Hybrid Sizing Method for Analog Integrated Circuits

Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1. doi:10.1109/tcad.2020.3025068 

Abstract: Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this paper, a two-phase hybrid sizing method for high performance analog circuits is proposed. It consists of gm/ID-based device characterization, circuit modeling, sensitivity-based constraints for LDEs, and mixed-integer nonlinear programming in the first phase, and many-objective evolutionary algorithm (many OEA) based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the gm/ID design methodology. Then the LDE parameters that are linked to the normalized DC current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floor plan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.

Fig: Module-level of the LDE-aware gm/ID EA two-phase synthesis flow

Thanks to the contribution of the EKV model [1], inversion coefficient (IC) can be used to indicate the biasing inversion level of a MOSFET. This helped Binkley et al. [2] change the design freedom from the conventional W, L, and ID to IC, L, and ID. Since IC is related to DC bias, device geometry, and device characteristics (e.g., gm/ID), it can reflect performance tradeoff (e.g., intrinsic gain vs. bandwidth) of a single MOSFET. In [3], bias information rather than gm/ID parameters was set as variables, while a small-scale LUT was built to find MOSFET aspect ratio (i.e., W/L) and eventually W.

Aknowlegement: This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC), Canada Foundation for Innovation (CFI), Research and Development Corporation (RDC) of Newfoundland and Labrador, and Memorial University of Newfoundland.

References:

1. C. Enz, F. Chicco, and A. Pezzotta, “Nanoscale MOSFET modeling: Part 1: The simplified EKV model for the design of low-power analog circuits,” IEEE Solid-State Circuits Mag., vol. 9, no. 3, pp. 26–35, 2017.
2. D. M. Binkley, C. E. Hopper, S.D. Tucker, B.C. Moss, J. M. Rochelle, and, D. P. Foty, “A CAD methodology for optimizing transistor current and sizing in analog CMOS design,” IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 22 no. 2, pp. 225-237, 2003.
3. C.-W. Lin, P.-D. Sue, Y.-T. Shyu, and S.-J. Chang, “A bias-driven approach for automated design of operational amplifiers,” in Proc. Int.

[paper] oTFT Charge-Based Variability Model

Aristeidis Nikolaou, Ghader Darbandy, Jakob Leise, Jakob Pruefer, James W. Borchert, Michael Geiger, Hagen Klauk, Benjamin Iñiguez, Fellow, IEEE,

and Alexander Kloes, Senior Member, IEEE

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors 

Due to Carrier-Number and CorrelatedMobility Fluctuation

in IEEE TED (early access), DOI: 10.1109/TED.2020.3018694.

Abstract: In this study, a consistent analytical chargebased model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-numberfluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

Fig: a) Cross section of the organic TFTs fabricated in the inverted coplanar (bottom-gate, bottom-contact) architecture. b) Transistor channel divided into a noisy element between positions x and x + δx and two noiseless transistors of channel lengths x and L − x, respectively. c) Small-signal representation.

Acknowledgment: This work was supported in part by the German Federal Ministry of Education and Research “SOMOFLEX” under Grant 13FH015IX6 and in part by the German Research Foundation (DFG) under Grant KL 1042/9-2 (SPP FFlexCom). The authors would like to thank AdMOS GmbH for support.

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