[mos-ak] Fwd: MOS-AK / IEEE-EDS-MQ / SSB-MOS Workshops at THM - Deadline extended

Dear colleagues and friends, 

please note that the registration deadline for the

Joint Spring MOS-AK Workshop and 

Symposium on Schottky Barrier MOS (SB-MOS) devices with 

IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies" 

has been extended. 

The event hosted by THM will take place in Zoom as live presentations Sept. 29 to Oct. 1. 

Please register until Sept. 25 by use of IEEE vTools: 

https://meetings.vtools.ieee.org/m/205571
The registration is for free. 

Preliminary program: 

https://ssbmos.blogspot.com/p/programm-2020.html and 

http://www.mos-ak.org/giessen_2020

Registered attendees will receive the Zoom link for the event a few days before via email from vTools.

Important new dates: 
1st Event Announcement: Aug. 2020 
2nd Event Announcement: Sept. 2020 
Final Workshop Program: Sept. 2020
Registration deadline (extended): Sept. 25, 2020
"Spring" MOS-AK Workshop: Sept. 29/30, 2020 
IEEE MQ: Sept. 30/Oct. 1, 2020
Symposium SB-MOS devices: Oct. 1, 2020

Best regards

Alexander Kloes

_____________________________________________________________

Prof. Dr.-Ing. Alexander Kloes

 

Technische Hochschule Mittelhessen - University of Applied Sciences

Department Electrical Engineering and Information Technology

Spokesperson of Competence Center Nanotechnology and Photonics

Director of Doctoral Theses at Universitat Rovira i Virgili, Tarragona

Wiesenstrasse 14

D-35390 Giessen

Germany

E-mail: alexander.kloes@ei.thm.de

Web: go.thm.de/dmrg-en and www.thm.de

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#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi https://t.co/ieDnhSHxZh

#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi pic.twitter.com/ieDnhSHxZh

— Wladek Grabinski (@wladek60) September 22, 2020

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from Twitter https://twitter.com/wladek60

September 22, 2020 at 11:20AM
via IFTTT

[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.

Si2 VAMPyRE: compact model parser and checker

Si2 #Compact #Model #Coalition Offers VAMPyRE, the software is a standalone compact model parser and checker written in Python, to Members and Developers https://t.co/vPQWlcQ99l pic.twitter.com/gbUq5nBFOA

— Wladek Grabinski (@wladek60) September 21, 2020

from Twitter https://twitter.com/wladek60

September 21, 2020 at 05:18PM
via IFTTT

[tutorial] next generation 3D nano device simulator

Single-electron transistor - laterally defined quantum dot - 3D Tutorial

Stefan Birner

https://www.nextnano.com

Single-electron transistor - laterally defined quantum dot In this tutorial, we simulate an AlGaAs/GaAs heterostructure grown along the z direction. This structure leads to a two-dimensional electron gas (2DEG). By appying a gate voltage on top of the structure in the (x,y) plane, one is able to deplete the 2DEG and a laterally defined QD is formed. By adjusting the gate voltage, one is able to tune the number of electrons that are inside the QD.

This figure shows the conduction band edge Ec(x,y) and the electron density n(x,y) for the 2DEG plane, i.e. at z = 8 nm below the GaAs/AlGaAs heterojuntion. The geometry of the top gates is indicated by the blue regions. The following figure shows the calculated conduction band edge and the electron density of the heterostructure. The results are similar to Fig. 4 in paper [1].

The following figure shows two 2D slices through the lateral (x,y) plane at a distance of 8 nm below the AlGaAs/GaAs interface. In the middle, the electron density is shown. The electron density has been calculated classically. At the bottom, the conduction band edge is shown. The results are similar to Fig. 5 in paper [1]. At the top, the four gates are shown.

REF:

[1] A. Scholze, A. Schenk, W. Fichtner; Single-Electron Device Simulation; IEEE TED 47, 1811 (2000)