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Sep 17, 2020
Fwd: September 2020 Newsletter: Planet-Scale Processing of Silicates
[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell
Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell
Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne
and Manus Hayne
Scientific Reports volume 9, Article number: 8950 (2019)
DOI: 10.1038/s41598-019-45370-1
Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.
FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.
Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.
Sep 16, 2020
The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi https://t.co/TKw7mFqOcC
The Industry’s First SoC FPGA Development Kit Based on the #RISC-V Instruction Set Architecture is Now Available | Microchip Technology https://t.co/1CCwP6GR3h #semi pic.twitter.com/TKw7mFqOcC
— Wladek Grabinski (@wladek60) September 16, 2020
from Twitter https://twitter.com/wladek60
September 16, 2020 at 04:32PM
via IFTTT
Sep 15, 2020
FreePDK15: Process Design kit for 15-nm FinFETs
Development of a Predictive Process Design kit for 15-nm FinFETs: FreePDK15
Kirti Bhanushali, Chinmay Tembe, and W. Rhett Davis
arXiv:2009.04600v1 [cs.AR] 9 Sep 2020
Abstract: FinFETs are predicted to advance semiconductor scaling for sub-20nm devices. In order to support their introduction into research and universities it is crucial to develop an open source predictive process design kit. This paper discusses in detail the design process for such a kit for 15nm FinFET devices, called the FreePDK15. The kit consists of a layer stack with thirteen-metal layers based on hierarchical-scaling used in ASIC architecture, Middle-of-Line local interconnect layers and a set of Front-End-of-Line layers. The physical and geometrical properties of these layers are defined and these properties determine the density and parasitics of the design. The design rules are laid down considering additional guidelines for process variability, challenges involved in FinFET fabrication and a unique set of design rules are developed for critical dimensions. Layout extraction including modified rules for determining the geometrical characteristics of FinFET layouts are implemented and discussed to obtain successful Layout Versus Schematic checks for a set of layouts. Moreover, additional parasitic components of a standard FinFET device are analyzed and the parasitic extraction of sample layouts is performed. These extraction results are then compared and assessed against the validation models.
FIG: Middle-of-Line layers used as interconnects
Acknowledgment: The authors would like to thank Paul Franzon at NC State University. The authors would like to thank Mentor Graphics, since this project would not have been possible without their generous gift of supporting funds and Calibre licenses. The authors would also like to thank Tarek Ramadan, Ahmed Hammed Fathy, Omar El-Sewefy, Ahmed El-Kordy, Hend Wagieh and the team at Mentor Graphics for development of the first set of design rules and their constant support.In addition, the authors would like to thank and acknowledge Alexandre Toniolo at Nangate for clarifying the vision of MOL layers. We would also like to thank Cadence designsystems for use of the virtuoso software and Synopsys Inc.for use of Pycell studio. The authors would also like to thanks Vikas Sharma for P-Cells, Vidyanandgouda Patil for design rule fixes and Namrata Sampat for help cleaning up the distribution.
Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020)
Respected All
On behalf of the organizing committee of the Science Academies Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020),
I am sharing separate Zoom Links for each day.
You are requested to register yourself for one or more sessions by registering separately.
Kindly forward this email to your friends, students and colleagues from all branches of science and engineering.
- Kindly join at least 15 minutes before the session.
- Letter of attendance for each day will be provided at the end of the session.
September 15, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_JF5EVXqsTBCcHLIuL2e7dA)
- 04:00 pm – 05:00 pm - The Lead Halide Perovskites: Photoluminescence and Charge Carrier Dynamics - Professor Anunay Samanta, FASc, FNASc, FNA, Sr. Professor and J.C. Bose National Fellow (DST), School of Chemistry, University of Hyderabad
- 05:00 pm – 06:00 pm - Interdisciplinary Education for Science and Innovation - Professor Sourav Pal, FASc, FNASc, FNA, Director, Indian Institute of Science Education & Research, West Bengal
September 16, 2020 (Zoom Link: https://zoom.us/webinar/register/WN_hbdn7CqUQMqWUeyaW7qJTA)
- 06:00 pm – 07:00 pm Electronic Cash, Cryptocurrencies and Smart Contracts - Professor Rudrapatna Kallikote Shyamasundar, FASc, FNA, FNASc, FNAE, FIEEE, FTWAS, Distinguished V Professor, Computer Science & Engineering Department, IIT Powai
- 06:00 pm – 07:00 pm - Indian Healthcare, Digital Transformation, and COVID-19 - Dr Anurag Agrawal, FNA, Director, CSIR-Institute of Genomics and Integrative Biology, Mall Road, Delhi University
- 07:00 pm – 08:00 pm - Responsibilities and opportunities for academics in the context of current pandemic - Dr. Rakesh K Mishra, FASc, FNASc, FNA, Director, CSIR-Centre for Cellular & Molecular Biology, Hyderabad
- 06:00 pm – 07:00 pm - Continued fraction expansions of complex numbers - Prof. Shrikrishna Gopalrao Dani, FASc, FNA, FNASc, Distinguished Professor, Centre for Excellence in Basic Sciences, University of Mumbai, Maharashtra
- 07:00 pm – 08:00 pm - C.R.Rao and Mahalanobis' Distance - Prof. Probal Chaudhuri, FASc, FNA, FNASc, Theoretical Statistics and Mathematics Unit, Indian Statistical Institute, Kolkata
- 06:00 pm – 07:00 pm - Future Geosciences and Opportunities - Prof. Ashok Kumar Singhvi, FASc, FNA, FNASc, FTWAS, Honorary Scientist, Atmospheric, Molecular & Optical Physics Divn., PRL, Gujarat
- 07:00 pm – 08:00 pm - Glasses and other amorphous solids - Professor Srikanth Sastry, FASc, FNASc, FNA, Theoretical Sciences Unit, JNCASR, Bangalore, Karnataka
with regards
Dr. Manoj Saxena | डॉ मनोज सक्सेना
Associate Professor | सह - आचार्य
Department of Electronics | इलेक्ट्रॉनिक्स विभाग
Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज
University of Delhi | दिल्ली विश्वविद्यालय
Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८
India | भारत
Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com
ORCID Webpage : http://orcid.org/0000-0002-9368-4194
Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200
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Publons Profile: https://publons.com/researcher/1341187/manoj-saxena
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