[paper] Unified Analytical Model for SOI LDMOS

Baoxing Duan, Jingyu Xing, Ziming Dong and Yintang Yang¹ (Senior Member, IEEE)

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

IEEE J-EDS, vol. 8, pp. 686-694, 2020

DOI: 10.1109/JEDS.2020.3006293

¹Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China

Abstract: The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

FIG: Cross-sectional view of electric field modulated SOI LDMOS

Acknowledgment: This work was supported in part by Science Foundation for Distinguished Young Scholars of Shaanxi Province under Grant 2018JC-017, and in part by the 111 Project under Grant B12026.

Fwd: IEEE-EDS SCV/SF Chapter July Distinguished Lecture (Webex only)

Dear IEEE EDS members in Santa Clara Valley/San Francisco Chapter

Please note that this seminar is now WEBEX participation only. 

Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmWave Wireless Connectivity Solution

Speaker: Dr. Anirban Bandyopadhyay, Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA

Friday, July 24, 2020 at 12PM – 1PM PDT

WEBEX ONLY: Click Here to Attend

Abstract:

The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.

Speaker Bio:

Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC's. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We promise no spam and try to minimize email. You can unsubscribe easily.

http://site.ieee.org/scv-eds/subscribe/

---

To unsubscribe from the EDS-CHAP-SCV list, click the following link: https://listserv.ieee.org/cgi-bin/wa?SUBED1=EDS-CHAP-SCV&A=1

[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 

"Advanced Field Effect Transistors: Design, Fabrication and Applications"

Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,

Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.

However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.

There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

[read more...]

#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q #opensource https://t.co/oLachje3z4

#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q#opensource pic.twitter.com/oLachje3z4

— Wladek Grabinski (@wladek60) July 17, 2020

from Twitter https://twitter.com/wladek60

July 17, 2020 at 06:25PM
via IFTTT

[paper] Compact Modeling of NC FDSOI FETs

C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020

DOI: 10.1109/TED.2020.2994018

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI FET. (c) Gate-stack of MFMIS FDSOI FET.

Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.