Nov 1, 2019

#paper: Versatile model for the contact region of organic thin-film transistors A.Romeroab J.Gonzáleza M.J.Deenc J.A.Jiménez-Tejadab https://t.co/9wJwjKlu69 https://t.co/rFCp02RFEF


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November 01, 2019 at 03:56PM
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#Indian #startups have raised a record $11.3B this year – TechCrunch https://t.co/qiJE1BnlV1 #paper https://t.co/yDn1H7aiPJ


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November 01, 2019 at 03:03PM
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Openings for Research Staff and PhD Scholarships Singapore-MIT Alliance for Research and Technology Low Energy Electronic Systems - Phase II 1 CREATE Way 09-01/02 CREATE Tower; 01-13 Enterprise Wing Singapore 138602 https://t.co/hUapbZCyAU #paper https://t.co/VNFXBjlxRY


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November 01, 2019 at 02:01PM
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Program to convert Sandia’s Albuquerque, N.M.-based fab from 150mm (6-inch) to 200mm (8-inch) wafer sizes. As part of the move, Sandia is converting its 0.35-micron (350nm) rad-hard process from 150mm to 200mm. The process is called CMOS7 https://t.co/JrWmF8BV0a #paper https://t.co/FJasxsp3s1


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November 01, 2019 at 01:55PM
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Oct 30, 2019

[mos-ak] [2nd Announcement and C4P] 12th International MOS-AK Workshop, Silicon Valley, DEC.11, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
12th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop which will be organized at Silvaco HQ on Dec. 11, 2019 (co-located with the IEDM and CMC Meetings)

Planned 12th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: 
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source (FOSS) TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2019
  • 2nd Announcement - Oct. 2019
  • Final Workshop Program - Nov. 2019
  • MOS-AK Workshop: Dec. 11, 2019
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)
WG301019

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