Demystifying #SPICE #noise #simulation https://t.co/er91QH6ub7 #paper

Demystifying #SPICE #noise #simulation https://t.co/er91QH6ub7 #paper

— Wladek Grabinski (@wladek60) December 2, 2017

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December 02, 2017 at 08:54PM
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[paper] Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Mike Brinson, and Vadim Kuznetsov

International Journal of Microelectronics and Computer Science

2017, Volume 8, Number 1 

ISSN 2080-8755 / eISSN 2353-9607

Abstract—The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It’s inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice [read more...]

Fig: EKV2.6 Qucs-S long channel static I/V model test bench and typical simulated I/V output characteristics as Qucs-S Equation-Defined Model

Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper

Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper

— Wladek Grabinski (@wladek60) November 25, 2017

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November 26, 2017 at 12:25AM
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#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf

#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf

— Wladek Grabinski (@wladek60) November 25, 2017

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November 25, 2017 at 06:09PM
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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper

— Wladek Grabinski (@wladek60) November 25, 2017

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November 25, 2017 at 04:31PM
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