[mos-ak] [2nd Announcement and Call for Papers] 15th MOS-AK ESSDERC/ESSCIRC Workshop

MOS-AK ESSDERC/ESSCIRC Workshop
http://www.mos-ak.org/leuven_2017/
September 11, 2017 Leuven
2nd Announcement and Call for Papers

Together with the ASCENT Network represented by Profs Jim Greer and Nicolas Cordero as well as  International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 15th MOS-AK Compact Modeling Workshop which will be organized for consecutive 15time as in integral part of the ESSDERC/ESSCIRC Conference in Leuven on Sept.11, 2017.

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - March 2017
• Call for Papers - June 2017
• Final Workshop Program - August 2017
• MOS-AK Workshop - Sept.11, 2017

Venue: Leuven (B) <http://www.esscirc-essderc2017.org/venue>

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Speakers: (tentative list in alphabetic order)

• Nicolas Cordero, Tyndal (IRL)
• Denis Flandre, CUL (B)
• Jim Greer, Tyndal (IRL)
• Benjamin Iniguez URV (SP)
• Marcelo Pavanello, FEI (BR)
• Jean-Pierre Raskin, CUL (B)
• Wim Schoenmaker, Magwel (B)
• Chika Tanaka, Toshiba (J)
• Ashkhen Yesayan, IRPhE (AM)

Prospective authors should submit abstract online

Manuscript submission deadline: 31sth July 2017 (Monday)
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration

using online registration form <http://www.esscirc-essderc2017.org/howtoregister>
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG080717

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[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

Multiple Honors for E3S Theme Leader, Professor Tsu-Jae King Liu

(March 1, 2017) –   The Center for Energy Efficient Electronics Science is proud to announce Prof. Tsu-Jae King Liu has been named a newly elected member of the National Academy of Engineering. Prof. King Liu, who leads the E³S Nanomechanics theme was elected this year as one of only three members from UC Berkeley to this highest professional honor to an engineer. Last year in August, Prof. King Liu has also been chosen to serve on the Board of Directors at Intel Corporation. She was welcomed by Intel Chairman Andy Bryant: “[Prof. King Liu] brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”In addition to this distinguished honor by Intel, last year the Semiconductor Research Corporation (SRC) announced Prof. King Liu has been selected to receive the 2016 SRC Aristotle Award. This esteemed award was created by the SRC Board of Directors in March 1995 with the intent "to acknowledge outstanding teaching in its broadest sense, emphasizing student advising and teaching." Heartiest congratulations from the entire E³S community to Prof. King Liu for these prestigious honors!

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs

Abhijeet Walkea^a, Garrett Schlenvogtb^b, Santosh Kurineca^a

^aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA

^bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< I_OFF <50pA/μm) and ultralow power (ULP) (I_OFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (I_OFF), transconductance (g_m), gate capacitance (C_gg) and intrinsic frequency (f_T). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Rising SOI tide lifts Soitec into profit

Soitec SA (Bernin, France), developer of the "smart cut" method of silicon-on-insulator (SOI) wafer production, has reported its first profit for many years and is preparing to invest in facilities in France and possibly Singapore to meet rising demand for SOI wafers...

https://shar.es/1BtAZy


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