[call for papers] 2017 IEEE S3S Conference

Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.

Important Dates

Paper Submission Deadline: May 22, 2017

Acceptance Notification: July 1, 2017

The conference at a glance

Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions

Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

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Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes • Device Physics, Characterization and Modeling • Device/Circuit Integration • SOI Design, Circuits and Applications	• Non-Digital Devices and Applications (RF, HV, Photonics, NEMS, MEMS, Analog...) • New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors • Biomedical Devices • Low-Voltage Handheld/wireless systems • Ultra-Low-Power Digital Computation • Analog and RF Technologies	• Low Voltage Memory Technologies • Energy Harvesting Techniques • Asynchronous Circuits • Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing • Fabrication Techniques and Bonding Methods • Design and Test Methodologies • Processes for Multi Wafer Stacking • 3D IC EDA and Design Technology	• Heterogeneous Structures • 3D Manufacturing and Logistics • Reliability of 3D Circuits • Fault Tolerant 3D Designs

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Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

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Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
REF: 

[1] HiSIM 2. Y. Z: Surface-Potential-Based RF MOSFET Model for Circuit Simulation

[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper

[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper

[4] HiSIM_HV Y. Z: Surface-Potential-Based HV/LD_MOSFET Model for Circuit Simulation

[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013

[paper] Model for Organic Thin-Film Transistor

Physically Based Compact Mobility Model for Organic Thin-Film Transistor

T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch and H. J. Mattausch

in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2057-2065, May 2016.

doi: 10.1109/TED.2016.2540653

Abstract: A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy (EF) movement in the bandgap (Eg) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside Eg. The Poole-Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model [read more...]

Workshop on biomedical applications at EPFL Lausanne

Data communication and remote powering for biomedical applications 

Workshop organized by Prof. Catherine Dehollain and Dr. Maria-Alexandra Paun
on February 24, 2017 at 09:00-17:00 in Room BC 01, EPFL Lausanne

Workshop Program

Time	Invited Speaker	Presentation Title
09:00-09:35	Professor Catherine DEHOLLAIN, EPFL, Lausanne, RF IC group	“Remotely powered sensor networks for medical applications”
09:35-10:10	Dr. Maria-Alexandra PAUN, EPFL, Lausanne, RF IC group	“Modeling and analysis of antennas in cochlear implants”
10:10-10:45	Dr. Gürkan YILMAZ, EPFL, Lausanne, RF IC group	“Wireless Power Transfer and Data Communication for Intracranial Neural Implants. Case Study: Epilepsy Monitoring”
Coffee Break (30 minutes)
11:15-11:50	Dr. Mehrdad GHANAD, EPFL, Lausanne, RF IC group	“Remotely-Powered Batteryless Implantable Local Temperature Monitoring System for Freely Moving Mice”
11:50-12:25	Francesca STRADOLINI, EPFL, Lausanne, LSI laboratory	“On-line monitoring of aesthetics during surgery: opportunities and challenges”
12:25-13:00	Professor Adrian M. IONESCU, EPFL, Lausanne, Nanolab laboratory	“Wearable biosensors and their applications in future digital health”
LUNCH (90 minutes)
14:30-15:05	Dr. Wladek GRABINSKI, MOS-AK Association (EU)	“FOSS TCAD/EDA simulation tools with molecular/bio/med modeling examples”
15:05-15:40	Dr. Albrecht LEPPLE-WIENHUES, Valtronic Technologies SA	“Ear infection, drug injectors and blood donation: innovative medical device development”
15:40-16:15	Dr. Qing WANG, CHUV, Lausanne	“Development of a flow-through telemetry implant for monitoring cardiovascular blood pressure in small rodents and human”
16:15-16:50	Professor Philippe RYVLIN, CHUV, Lausanne	“Wearable devices for neurological diseases: Towards more rigorous clinical evaluation”
Concluding remarks (10 minutes)

[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci¹ and Christian Tschoban^2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
²Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017

Abstract

RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]