Sedemos News

Jul 8, 2016

An improved model for substrate in RF SOI MOSFET varactor https://t.co/iK16GyX82y #papers #feedly

An improved model for substrate in RF SOI MOSFET varactor https://t.co/iK16GyX82y #papers #feedly
— Wladek Grabinski (@wladek60) July 8, 2016

from Twitter https://twitter.com/wladek60

July 08, 2016 at 10:12PM
via IFTTT

[mos-ak] [2nd Announcement and Call for Papers] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

MOS-AK ESSDERC/ESSCIRC Workshop

Lausanne September 12, 2016
2nd Announcement and Call for Papers

Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and local workshop coordinator Jean-Michel Sallese, EPFL (CH) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 14th consecutive MOS-AK ESSDERC/ESSCIRC Workshop which will be held at Swisstech Convention Centre in Lausanne on September 12, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

Call for Papers - June 2016

2nd Announcement - July 2016

Final Workshop Program - August 2016

MOS-AK Workshop - Sept.12 2016

Venue:

Swisstech Convention Centre EPFL
Route Louis-Favre 2
CH-1024 Ecublens

Topics to be covered include the following among other related to the compact/SPICE modeling :

Advances in semiconductor technologies and processing
Compact Modeling (CM) of the electron devices
Verilog-A language for CM standardization
New CM techniques and extraction software
Open Source TCAD/EDA modeling and simulation
CM of passive, active, sensors and actuators
Emerging Devices, TFT, CMOS and SOI-based memory cells
Microwave, RF device modeling, high voltage device modeling
Nanoscale CMOS devices and circuits
Technology R&D, DFY, DFT and reliability/ageing IC Designs
Foundry/Fabless Interface Strategies

Speakers: tentative list of MOS-AK Experts:

Marco Bellini, ABB (CH)
Mike Brinson, LondonMet, (UK)
Matthias Bucher, TUC (GR)
Mansun Chan, UST (HK)
James Greer, ASCENT, Tyndall (IE)
Benjamin Iniguez, URV (SP)
Alexander Kloes, THM (D)
Muhammad Nawaz, ABB (SE)
Denis Rideau, ST (F)
Jean-Michel Sallese, EPFL (CH)
Andrei Vladimirescu, UCB (USA); ISEP (FR); Keynote
Lining Zhang, UST (HK)

Online MOS-AK Abstract Submission:
Prospective authors should submit an abstract to abstracts@mos-ak.org

Online Workshop Registration:

http://esscirc-essderc2016.epfl.ch/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Jul 8, 2016

An improved model for substrate in RF SOI MOSFET varactor https://t.co/iK16GyX82y #papers #feedly

[mos-ak] [2nd Announcement and Call for Papers] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

Jul 6, 2016

"Measurement and analysis techniques for device agnostic electrical cha" #papers by James E Moore https://t.co/ryg6hgFn5f

Jul 1, 2016

Dual-Gate JFET #Modeling https://t.co/Cwroa516sK

Tutorial on Signal Processing in Linux with Octave https://t.co/Lzoeytzqwt #todo #feedly #papers

Sedemos Arch