Jan 22, 2016

Analytical #Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors https://t.co/ox0DFIspyF


from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:59PM
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Compact #Modeling of Magnetic Tunneling Junctions https://t.co/sl9NaOEg4G


from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:52PM
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Parasitic Capacitance Analytical #Modeling for Sub-7-nm Multigate Devices https://t.co/z8Q8IcuINM


from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:47PM
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Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices #modeling https://t.co/9Q50HGFkni


from Twitter https://twitter.com/wladek60

January 22, 2016 at 02:44PM
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Jan 19, 2016

FOSDEM 2016 EDA Devroom

FOSDEM 2016: EDA Devroom
Room: AW1.121 
Saturday, 30 January 2016

Software developers have a much easier time sharing their developments than hardware designers. When you put a piece of code on the Web, you don't ask yourself if others will have the freedom and resources to access a text editor to look at it and modify it, or a compiler or interpreter to have the code do something useful. The landscape for hardware designs is more complicated. The dominant design and simulation tools are proprietary, and there is not even a de-facto proprietary standard format to share designs. The Electronic Design Automation (EDA) Devroom looks at recent progress in Free CAD/EDA Tools for hardware design and simulation, and serves as a meeting place for discussion about future collaborations and FOSS developments. Come and see how some of these tools are actually catching up, and sometimes even more, in terms of features and quality.

[EDA Devroom Detailed Agenda]