| Successful candidates for this position will have:. Experience with Shell Scripts (Perl, Unix, Batch, Python, etc.).... |
Aug 21, 2013
Semiconductor Device Characterization Intern Job
Aug 18, 2013
Semiconductor Device Characterization Engineer jobs
Interacts with other groups such as Design, Process, System, Reliability, and FA. 5+ years of related hands-on industrial experience.... 5+ years of related hands-on industrial design experience. Hands-on experience with device physics, device process, device characterization, and systems.... Possess working knowledge of semiconductor device development processes. Semiconductor Research and Development Process Improvement Engineer, IBM Corporation,... |
Aug 13, 2013
Fwd: 4 new Semiconductor Device Characterization Engineer jobs
4 new jobs found
| Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface... GLOBALFOUNDRIES - Malta, NY Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;.... Experience would be obtained through your educational level research and/or relevant job/internship experiences.... Quantum Solution - Sunnyvale, CA Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, ).... |
Aug 8, 2013
[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel
Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th consecutive MOS-AK ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.
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The final workshop program as well as all further details and updates are on-line: <http://www.mos-ak.org/bucharest/ >
MOS-AK Workshop Program
| 9:00 - 12:00 | Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA) |
| O_1 | Welcome and Workshop Opening W. Grabinski MOS-AK Group (EU) |
| T_2 | SPICE - MOS-AK Keynote Larry Nagel Omega Enterprises Consulting (USA) |
| T_3 | NGSPICE: recent progresses and future plans Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning** *DIET - Sapienza University of Roma (I), ** NGSPICE Development Team |
| T_4 | KCL and Linear/NonLinear Separation in NGSPICE Francesco Lannutti DIET - Sapienza University of Roma (I) and NGSPICE Development Team |
| Coffee Break | |
| T_5 | Modeling Junction Less FETs Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut EPFL (CH) |
| T_6 | HiSIM-Compact Modeling Framework Hans Juergen Mattausch Uni. Hiroshima (J) |
| P_7 | The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur***** *State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA) |
| 12:00 -13:00 | Lunch Break |
| 13:00 -16:00 | Afternoon Session - Chair: W. Grabinski, MOS-AK Group |
| T_8 | State of the Art Modeling of Passive CMOS Components Bernd Landgraf Infineon Technologies (A) |
| T_9 | Compact I-V Model of Amorphous Oxide TFTs Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira**** *URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX) |
| Coffee Break | |
| T_10 | Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK) |
| T_11 | A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs Matthias Bucher, Rupendra Sharma Technical University of Crete, Chania, (GR) |
| T_12 | Towards wide-frequency substrate model of advanced FDSOI MOSFET Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre UCL (B) |
| 16:00 | End of the MOS-AK Workshop |
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Jul 8, 2013
[repost nanobuff] On compact modeling
Posted on June 27, 2013 on nanobuff
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"While the modeling industry is full of software solutions for all sorts of things in the operation of electronics from the very low to the very high level, there seems to be very sparse tools for simulating radiation effects. This would be normal if there was little interest or public research on the subject, but that is not the case. The models are out there, most of the basic concepts have been examined lots of decades ago, so what is stopping the industry? I really don’t know and I will not even try to answer.
Having said that, I would also like to state that compact modelling, in the case of radiation effects, is at least beneath me. I recently found this old compact modelling project. It is like a plugin to the Silvaco software. How would a compact modelling platform work in the ever-reducing dimensions of today? Things get fairly uncertain below 0.1 µm gate lengths. We need 3D, we need quantum models etc. just for the operation. And for the radiation part? That is now a materials science problem, I guess. And if you decide to go Monte Carlo, that’s even more demanding. The problem seems to be a “chicken and egg” one. We need more processing power to be able to simulate our next generation electronics that will give us more processing power."
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