Fwd: 4 new Semiconductor Device Characterization Engineer jobs

Semiconductor Device Characterization Engineer jobs

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4 new jobs found

Applications Engineer Intersil 11 reviews - Milpitas, CA Knowledge of analog and mixed signal board level design including PCB layout guidelines a strong plus. Knowledge of both analog and digital video interface... Intersil - 11:04 PM Process Engineer GLOBALFOUNDRIES - Malta, NY Technology related Bachelor's degree with 6 years experience ;. or Master's degree plus 5 years experience in process technology development area;.... GLOBALFOUNDRIES - 7:22 PM Reliability DA Engineer - EM/SH/ESD - 717531 Intel 325 reviews - Hillsboro, OR Experience would be obtained through your educational level research and/or relevant job/internship experiences.... Intel - 2:45 PM Sr Engineer - CMOS 5Gb/s+ (AMD-26317) Quantum Solution - Sunnyvale, CA Excellent proficiency of Cadence's custom IC design environment, analog/mixed signal circuit simulation (Spectre, Hspice, Ocean scripting, ).... Quantum Solution - 4:53 AM

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[mos-ak] [Final Program] 11th MOS-AK ESSDERC ESSCIRC Workshop with the keynote speaker Larry Nagel

Together with Prof. Andrei Vladimirescu, R&D Scientific Coordinator, the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th consecutive MOS-AK ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.  

The final workshop program as well as all further details and updates are on-line: <http://www.mos-ak.org/bucharest/> 

- with regards - WG (for the MOS-AK/GSA Committee) 

MOS-AK Workshop Program

9:00 - 12:00	Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA)
O_1	Welcome and Workshop Opening W. Grabinski MOS-AK Group (EU)
T_2	SPICE - MOS-AK Keynote Larry Nagel Omega Enterprises Consulting (USA)
T_3	NGSPICE: recent progresses and future plans Paolo Nenzi*, Francesco Lannutti*, Robert Larice**, Holger Vogt**, Dietmar Warning** *DIET - Sapienza University of Roma (I), ** NGSPICE Development Team
T_4	KCL and Linear/NonLinear Separation in NGSPICE Francesco Lannutti DIET - Sapienza University of Roma (I) and NGSPICE Development Team
	Coffee Break
T_5	Modeling Junction Less FETs Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut EPFL (CH)
T_6	HiSIM-Compact Modeling Framework Hans Juergen Mattausch Uni. Hiroshima (J)
P_7	The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model Valentin Turin*, Gennady Zebrev**, Sergey Makarov***, Benjamin Iniguez****, and Michael Shur***** *State University-ESPC (RU),**MEPHI (RU),***SYMICA Inc (RU),****URV (SP),*****RPI (USA)
12:00 -13:00	Lunch Break
13:00 -16:00	Afternoon Session - Chair: W. Grabinski, MOS-AK Group
T_8	State of the Art Modeling of Passive CMOS Components Bernd Landgraf  Infineon Technologies (A)
T_9	Compact I-V Model of Amorphous Oxide TFTs Benjamin Iniguez*,Alejandra Castro-Carranza* , Muthupandian Cheralathan* , Slobodan Mijalkovic**, Pedro Barquinha***, Elvira Fortunato***, Rodrigo Martins***,Magali Estrada****, and Antonio Cerdeira**** *URV (SP), **Silvaco Ltd (UK), ***UNL(P), ****CINVESTAV (MEX)
	Coffee Break
T_10	Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK)
T_11	A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs Matthias Bucher, Rupendra Sharma Technical University of Crete, Chania, (GR)
T_12	Towards wide-frequency substrate model of advanced FDSOI MOSFET Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre UCL (B)
16:00	End of the MOS-AK Workshop

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[repost nanobuff] On compact modeling

Posted on June 27, 2013 on nanobuff

"While the modeling industry is full of software solutions for all sorts of things in the operation of electronics from the very low to the very high level, there seems to be very sparse tools for simulating radiation effects. This would be normal if there was little interest or public research on the subject, but that is not the case. The models are out there, most of the basic concepts have been examined lots of decades ago, so what is stopping the industry? I really don’t know and I will not even try to answer.

Having said that, I would also like to state that compact modelling, in the case of radiation effects, is at least beneath me. I recently found this old compact modelling project. It is like a plugin to the Silvaco software. How would a compact modelling platform work in the ever-reducing dimensions of today? Things get fairly uncertain below 0.1 µm gate lengths. We need 3D, we need quantum models etc. just for the operation. And for the radiation part? That is now a materials science problem, I guess. And if you decide to go Monte Carlo, that’s even more demanding. The problem seems to be a “chicken and egg” one. We need more processing power to be able to simulate our next generation electronics that will give us more processing power."

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Third Berkeley Symposium on Energy Efficient Electronic Systems

Time: October 28 - 29, 2013
Place: Sutardja Dai Hall, UCB, California, USA

Message from Symposium Organizers

Once again, we look forward to hosting another Berkeley Symposium on Energy Efficient Electronic Systems, a forum that we founded in 2009. Biennially, we bring together researchers who are working on breakthrough improvements in energy efficiency for information processing systems. Our goal is that the Symposium continue to be a venue for the attendees to gain an integrated perspective of the challenges and advances in this domain of technology through sessions that cover the entire food chain, from devices to systems. As in the two previous symposia, we expect that the academic setting of UC Berkeley will encourage open exchanges of ideas, and foster closer cooperation and collaborations among the researchers.

For the first time, we welcome IEEE Electronic Devices Society as a technical co-sponsor. Also new, the 2013 Organizing Committee is issuing a Call for Papers. These changes are intended to broaden participation at the Symposium, thereby furthering the Symposium's goal of fostering information exchanges and collaborations.

We look forward to seeing you at the 3rd Berkeley Symposium on Energy Efficient Electronic Systems.

Eli Yablonovitch, Co-Chair, Organizing Committee
Jeffrey Bokor, Co-Chair, Organizing Committee

[Symposium Link]

URSI-C Commission Workshop (Kawasaki)

Theme: "Simulation Techniques for wireless communication integrated circuit design" 

Sponsorship:

• URSI-C committee  

Sponsored by:

• IEEE MTT-S Japan Chapter 
• IEEE AP-S Japan Chapter 
• IEEE VT-S Japan Chapter 
• IEEE SSC-S Japan Chapter 

Date and time: Friday, 12:30 to 16:30, July 05, 2013
Location:  Toshiba Science Museum (directions from Komukaitoshiba town)
Entry fee: Free

Program
12:15 - 12:30 Reception
12:30 - 13:15 Toshiba Science Museum tour
13:30 - 13:40 Opening Remarks Masahiro Morikura (Kyoto University)
13:40 - 14:20 "High frequency modeling of the MOSFET, including the process variation" Yoshitomi Sadayuki (Toshiba)
14:20 - 15:00 "Challenges and Solutions for RFIC Realization"  Sugaya Hidehiko (Cadence Japan)
15:00 - 15:10 Break (10 minutes)
15:10 - 15:50 "Methodology for substrate coupling analysis with high frequency accuracy" Sotiris Bantas (Helic, Inc.)
15:50 - 16:30 "Behavioral technology of RF transceiver circuit" Takahiro Kikuchi (Agilent Technologies)
16:30 Closing
17:30 - social gathering

[read more...]