Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond

From EDN:

Industry Need for Continued Scaling
Technological advances in transistor scaling have had a dramatic effect on consumer electronics and their corresponding use cases. In 1973, Motorola developed the first mobile phone, which weighed 2.5 pounds, was 9 inches long, had limited battery life and only allowed users to make and receive calls. Fast forward to today's mobile devices that fit in the palm of your hand, with batteries that last all day and more computing power than ever thought possible.
While it has taken 40 years to come this far, innovation has been exceptionally rapid over the course of the past 10 years, and consumer expectations have accelerated at a similar pace. What sort of features and computing capabilities will we expect of our mobile devices five years from now? How about in 10 years? Future improvements largely hinge on the industry's ability to continue on the path of Moore's Law by producing ever-smaller transistors with ever-greater performance. Satisfactory scaling fulfills two core requirements: the need for smaller transistors that reduce costs and a parallel need for improved performance and lower power consumption.
To date, transistor scaling has continued in accordance with Moore's Law down to 32 nm. Engineering challenges, however, are forcing chipmakers to compromise performance and power efficiency in order to reach smaller nodes - unless they switch to new technologies that help better solve these challenges. Today, the semiconductor industry is starting to deploy such new technologies, largely relying on "fully-depleted" transistors for continued scaling and performance gains.
Fully Depleted Silicon Technology
A fully depleted (FD) transistor can be planar or tri-dimensional. In each case, in direct contrast with other technologies commonly used today, the current between source and drain is allowed to flow only through a thin silicon region, defined by the physical parameters of the transistor.
In the planar design of fully depleted technology, transistors are built flat on the silicon. For the three-dimensional alternative, manufacturers fabricate thin vertical "fins" of silicon in which current will flow from source to drain. Additionally, FD transistors can eliminate the need for implanting "dopant" atoms into the channel. These improvements help chipmakers secure gains in both energy efficiency and performance that are required from scaling silicon technology.

Figure 1: Top Left (1a): Cross-section of a conventional MOS transistor on bulk silicon, Top right (1b): Cross-section of a planar fully-depleted transistor (FD-SOI), Bottom (1c): Perspective view of a FinFET (one fin shown here), silicon-on-insulator and bulk silicon flavors. (*) Note: PTS in the bottom right diagram is Punch Through Stopper, which is a heavily doped barrier layer at the bottom of the fin. S is Source, G is Gate, D is Drain of CMOS transistors. Notional views only; dimensions are not to scale.

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IBM, GF, and Samsung offer a glimpse of chipmaking's future

Below is a slide showing GF' process tech roadmap for the next little while:

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13. ITG/GMM-Fachtagung Analog 2013

13. ITG/GMM-Fachtagung Analog 2013
4. - 6. März in Aachen
Entwicklung von Analogschaltungen mit CAE-Methoden

Die Registrierung ist eröffnet!

Call For Papers:

Programm und Anmeldeformular:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

Article first published online: 20 JUL 2012
by Maria-Anna Chalkiadaki1, Cédric Valla2, Frédéric Poullet2 and Matthias Bucher1 (1. Department of Electronic and Computer Engineering, Technical University of Crete, 73100 Chania, Greece and 2. Dolphin Integration, 38242 Meylan, France)

SUMMARY: This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models’ Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models.

Synopsys Accelerates Adoption of FinFET Technology with Delivery of Production-Proven Design Tools and IP

From YahooFinance: (see their page for the original post)



Synopsys, Inc. (SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced immediate availability of its comprehensive solution for FinFET-based semiconductor designs. The solution includes a range of DesignWare^®Embedded Memory and Logic Library IP; silicon-proven design tools from the Galaxy^™ Implementation Platform; and foundry-endorsed extraction, simulation and modeling tools. It also includes TCAD and mask synthesis products used by foundries for FinFET process development. The three-dimensional structure of FinFET devices represents a significant change in transistor manufacturing that impacts design implementation tools, manufacturing tools and design IP. Developed over a period of five years through engineering collaboration with leading foundries, research institutes and early adopters, Synopsys' FinFET solution delivers production-proven technologies to manage the change from planar to 3-D transistors. The full-line solution provides a strong foundation of EDA tools and IP needed to accelerate deployment of FinFET technology which offers improved power, performance and area for semiconductor designs.
"Synopsys continues to make significant investments to develop a complete solution for adoption of new process geometries and devices, including FinFETs," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Synopsys' extensive collaboration with all the partners within the FinFET ecosystem, including foundries, early adopters and research institutions, allows us to deliver best-in-class technologies and to enable the market to realize the full potential of this new transistor design."
"With our new 14nm-XM offering, we have accelerated our leading-edge roadmap to deliver a FinFET technology optimized for the expanding mobile market," said Gregg Bartlett, senior vice president, chief technology officer at GLOBALFOUNDRIES. "Collaboration with partners has been a key element of our ability to deliver this innovative FinFET solution. We have collaborated early with Synopsys in multiple areas, including modeling of the FinFET devices in HSPICE. We continue our collaboration to accelerate adoption of FinFET technology for our mutual customers."
"Our FinFET collaboration with Synopsys is key to maintaining our semiconductor leadership position," said Dr. Kyu-Myung Choi, senior vice president of System LSI Infrastructure Design Center, Samsung Electronics Co., Ltd. "Our foundry and semiconductor design expertise, combined with Synopsys' broad EDA tool and IP development experience enabled us to address FinFET-related challenges effectively. We continue to engage in strong collaboration to maximize the benefits of FinFET technology."
"Very early on, we successfully demonstrated the power and performance benefits of using FinFET 3-D transistors," said Dr. Chenming Hu, distinguished professor of microelectronics at University of California, Berkeley, widely regarded as the pioneer of FinFET technology. "To make these demonstrations possible, my team worked closely with Synopsys R&D on a number of areas including device simulation. We continue to collaborate with Synopsys to deliver more innovations for FinFET deployment."
FinFET-ready IP  Working closely with leading foundries for more than five years enabled Synopsys to gain design expertise and a deep understanding of IP architectures. This close collaboration has resulted in the successful deployment of Synopsys' DesignWare Embedded Memory and Logic Library IP solutions on FinFET to key customers. A broader range of IP is planned for development in 2013. The DesignWare Embedded Memory and Logic Library IP is architected to achieve the full benefits of the FinFET technology, delivering superior results in the areas of performance, leakage and dynamic power, and low voltage operation.
FinFET-ready Design Tools   The shift from planar to FinFET-based 3-D transistors is a significant change that requires close R&D collaboration among tool developers, foundries and early adopters to deliver a strong EDA foundation.  Developed through a multi-year collaboration with FinFET ecosystem partners, Synopsys' solution accelerates time to market of FinFET-based designs.  The comprehensive solution includes IC Compiler for physical design, IC Validator for physical verification, StarRC^™ for parasitic extraction, SiliconSmart for characterization, CustomSim^™ and FineSim for FastSPICE simulation and HSPICE^® for device modeling and circuit simulation.
FinFET-ready Manufacturing Tools    The small geometries and 3-D nature of FinFETs require new approaches to optimize device performance and leakage, and to address the effect of process variations. Target device performance and leakage is achieved through the optimization of the fin geometry, stress engineering and other factors. Process variations stem from random dopant fluctuations, line edge roughness, layout-induced stress and other sources, which together impact device and circuit performance. Synopsys has been collaborating with foundries on the Sentaurus^™ TCAD and Proteus^™ mask synthesis products to address these issues. The Sentaurus product line enables foundries to optimize FinFET processing and design devices that meet the performance and leakage targets while mitigating the impact of process variation. The Proteus product line provides foundries with a comprehensive solution for performing full-chip proximity corrections.