IEEE EDS Webinar: Physics and Technology of Advanced Solar Cells

This email is being sent on behalf of Paul Yu, EDS President,

and Meyya Meyyappan, EDS Vice President of Educational Activities.

Dear Colleague,

As part of our commitment to enhancing the value of membership in EDS, and to advancing the society's mission of fostering the professional growth of its members, we are pleased to invite you to attend a very special Webinar entitled Physics and Technology of Advanced Solar Cells presented by EDS Distinguished Lecturer and IEEE Fellow Prof. Vikram Dalal of Iowa State University.  More info available at http://www.mrc.iastate.edu/NewStaff/VikramDalal.htm.

The webinar will take place on Tuesday, February 14 at 3:00 PM Eastern Time (USA). Register for this event

This event is the follow-up to Prof. Dalal's successful talk entitled Introduction to Physics and Technology of Solar Cells which we presented in December.

Watch Replay.

(Note, you will need your IEEE web account login to register and access the video replay)

Title: Physics and Technology of Advanced Solar Cells
Abstract: The Shockley-Queisser (SQ) limit establishes an upper bound to the conversion efficiency of a single junction solar cell. In this talk, the various approaches to overcome the SQ limit will be discussed.  Multiple junction solar cells, multi-exciton solar cells, intermediate gap solar cells, and photon up and down conversion to increase efficiency beyond the SQ limit will also be addressed.  Multi-junction approaches have succeeded in producing highly efficient III-V solar cells.

In addition, Prof. Dalal will discuss thin film solar cells.  These cells, which use polycrystalline, amorphous or organic materials with inferior electronic properties, are now beginning to be widely used for both large scale utility power and for building-integrated and isolated products.  Prof. Dalal will address the special physical considerations needed to make efficient solar cells out of these materials, including new schemes for enhancing optical absorption and discuss the status of various technologies.

Attendance will be limited to 500 attendees, offered on a first come, first served basis.  As this event is being offered exclusively
to EDS members we request that you do not forward this invitation. Also, given the overwhelming response to our previous webinar,
it would help if you could team up with other EDS members at your institution and thus save a log in port.

Sincerely,

Paul Yu,
EDS President

Meyya Meyyappan,
EDS Vice President of Educational Activities.

IEEE, 445 Hoes Lane, Piscataway, NJ 08854 USA

< http://www.ieee.org/ >

 

New SPICE Model for Silicon Carbide Power MOSFET

Cree Releases SPICE Model for Silicon Carbide Power MOSFET

Behavior-based model enables power electronic design engineers to quantify benefits of silicon carbide MOSFETs in board-level circuit simulation

See the original press release, or read it here:

DURHAM, N.C., February 6, 2012 — Cree, Inc. (Nasdaq: CREE), a market leader in silicon carbide (SiC) power devices, has expanded its design-in support for the industry’s first commercially-available SiC MOSFET power devices with a fully-qualified SPICE model. Using the new SPICE model, circuit designers can easily evaluate the benefits Cree’s SiC Z-FET™ MOSFETs provide for achieving a higher level of efficiency than is possible with conventional silicon power switching devices for comparably-rated devices.

SiC MOSFETs have significantly different characteristics than silicon devices and therefore require a SiC-specific model for accurate circuit simulations. Cree’s behavior-based, temperature-dependent SPICE model is compatible with the LT spice simulation program and enables power electronics design engineers to reliably simulate the advanced switching performance of Cree CMF10120D and CMF20120D Z-FETs in board-level circuit designs.

Cree SiC MOSFETs are capable of delivering switching frequencies that are up to 10 times higher than IGBT-based solutions. Their higher switching frequencies can enable smaller magnetic and capacitive elements, thereby shrinking the overall size, weight and cost of power electronics systems.

This SiC MOSFET SPICE model adds to Cree’s comprehensive suite of design-in support tools, technical documentation, and reliability information to provide power electronics engineers with the design resources necessary to implement SiC power devices into the next generation of power systems.

The Cree SiC MOSFET SPICE model is available for download at www.cree.com/power/mosfet.asp. In addition, customers can download published specifications and detailed design guidelines and request samples. For more information about Cree’s SiC power devices, please visit www.cree.com/power.

About Cree
Cree is a market-leading innovator of semiconductor products for power and radio-frequency (RF) applications, lighting-class LEDs, and LED lighting solutions.

Cree's product families include LED fixtures and bulbs, blue and green LED chips, high-brightness LEDs, lighting-class power LEDs, power-switching devices and RF devices. Cree products are driving improvements in applications such as general illumination, electronic signs and signals, power supplies and solar inverters.

For additional product and company information, please refer to www.cree.com

This press release contains forward-looking statements involving risks and uncertainties, both known and unknown, that may cause actual results to differ materially from those indicated. Actual results may differ materially due to a number of factors, including customer acceptance of our products; the rapid development of new technology and competing products that may impair demand or render Cree’s products obsolete; and other factors discussed in Cree’s filings with the Securities and Exchange Commission, including its report on Form 10-K for the year ended June 26, 2011, and subsequent filings.

Cree is a trademark registered in the U.S. Patent and Trademark Office by and Z-FET is a trademark of Cree, Inc.

Media Contact:
Michelle Murray
Cree, Inc.
Corporate Communications
(919) 313-5505
michelle_murray@cree.com

SISPAD 2012, Denver, CO, USA, Call for Papers

Call for Papers The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of the leading-edge research and development results in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. Date and Location Conference date: September 5-7, 2012 Abstract submission deadline: April 1, 2012 Conference location: Sheraton Denver Downtown Hotel, Denver, Colorado, USA Webpage: http://www.ece.umd.edu/sispad2012 Topics Original papers are solicited in the following subject areas: Electronic Transport in Semiconductor Materials and Devices Device Modeling and Simulation Sensors, Biosensors and Electromechanical Systems Simulation Process and Equipment Modeling and Simulation Compact Models Physical-Level Circuit Simulation New Algorithms for Process and Device Modeling Simulation of Nano and Quantum Devices User Interfaces and Visualization Simulation of Power Devices Photovoltaics and Other Green Technologies The abstract should describe the nature of the presentation, together with references. The text must be single-spaced with 11pt or 12pt font. The abstract is limited to two pages including figures, tables and references. Abstracts should be submitted in PDF format. For more information, please visit: http://www.ece.umd.edu/sispad2012/

 

Execs gather at SEMI ISS

From Semiconductor Manufacturing and Design:

At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.

Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.

The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.

TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.

KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.

SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."

[mos-ak] C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18, 2012

C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18,
2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
JIIT, Noida (U.P.) India, March 16-18, 2012 with the tutorial on CMOS
technology and SPICE Models by Dr. N.D. Arora, Silterra, Malaysia.

List of the international modeling experts contributing to the MOS-AK/
GSA Workshop includes following names (in alphabetic order)
* Nanrian D. Arora, Silterra, Malaysia
* Navakanta Bhat, IISC Bangalore, India
* A.B. Bhattacharyya, JIIT Noida, India
* Mike Brinson, London Metropolitan University, UK
* Amitava Dasgupta, IIT Chennai, India
* Christian Enz, EPFL, Switzerland
* Tamilmani Ethirajan, IBM, India
* Thomas Gneiting, ADMOS, Germany
* Wladek Grabinski, MOS-AK/GSA
* Andre Juge, STM, France
* M. Jagdesh Kumar, IIT Delhi, India
* Shantanu Mahapatra, IISc, India
* Mitiko Miura-Mattausch, Hiroshima University, Japan
* Ramgopal Rao, IIT Mumbai
* Samar Saha, IEEE
* Manoj Saxena, University of Delhi, India
* Ehrenfried Seebacher, AMS, Austria
* Vaidyanathan Subramanian, IBM, India
* Xing Zhou, NTU, Singapore

The terms of participation:
* To register please visit the INAE website <http://inae.org/
seminar.htm> and complete the registration form
* Poster abstract submission with the deadline on Jan. 31, 2012.
Posters' abstract of maximum 300 words and paper of maximum 5 pages in
A4 size double spaced two columns should be submitted to Prof. AB
Bhattacharyya at <inaehq@gmail.com>

Intending participants and authors should also note the following
deadlines:
* Announcement and Call for Papers - Q4 2012
* Poster abstract submission deadline - Jan.31, 2012
* Final Workshop Program - Feb. 2012
* MOS-AK/GSA Workshop - March 16-18, 2012

Further details and updates: <http://www.mos-ak.org/india>
Email contact: <india@mos-ak.org>

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