[mos-ak] MOS-AK/GSA Washington DC on-line publications

MOS-AK/GSA Washington DC workshop on-line publications are available,
visit:
http://mos-ak.org/washington_dc/

I would like to thank all MOS-AK/GSA speakers for sharing their
compact modeling competence, R&D experience and delivering valuable
MOS-AK/GSA presentations. I am sure, that our modeling event in
Washington DC was a beneficial on to all the attendees as well as to
all MOS-AK/GSA Group.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
http://mos-ak.org/committee.html
––––––––––––––––––––––––––––––––––----------------
MOS-AK/GSA India March 16-17, 2012
<http://mos-ak.org/india/>
MOS-AK/GSA Dresden April 26-27, 2012
<http://mos-ak.org/dresden/>
MIXDES Special Modeling Sesion Warsaw May 24-26, 2012
<https://www.mixdes.org/Special_sessions.htm>
MOS-AK/GSA Bordeaux Sept.21, 2012
<http://goo.gl/bUrsp>
MOS-AK/GSA San Francisco Q4 2012
––––––––––––––––––––––––––––––––––----------------

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EPFL Post-doctoral/ experienced engineer position

Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at developing new technologies based on low power wireless communications, for communication between one intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain (RF IC group leader) is the scientific coordinator of this project. 

We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated circuits with strong practical experience in the following topics:

• Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks) 
• Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
• Design of CMOS power management circuits 
• Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications 
• Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc) 

The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.

• Starting date: as soon as possible. 
• Contract duration: 18 months 

Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain

C4P: 2012 IEEE Silicon Nanoelectronics Workshop

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society

Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices. Download the Call for Papers (PDF format) Further Information The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome. Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]

Price per transistor on a chip

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

25th ICMTS Conference

SAN DIEGO March 19-22, 2012

Day 1	Day 2	Day 3
08:45 Registration	09:00 Registration	09:00 Registration
08:45 Welcome	09:00 Process Characterization	09:00 Matching
08:55 Design Margin	11:10 RF	10:50 Capacitance
10:45 Variability	12:10 ICMTS 2013	12:10 Closing
11:45 Exhibitor Presentation	13:50 Parameter Extraction
13:45 MEMS	16:00 Stress
15:55 Poster

Note: This program is subject to change without notice. Final printed version of program will be available at the conference.