Analog/Mixed-Signal Behavioral Modeling

From Cadence... (see the original)

Analog/Mixed-Signal Behavioral Modeling – When to Use What

By Richard Goering on February 20, 2011

So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real  number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Also important is the modeling effort. Here we can see that conservative models require the most amount of effort. "You can potentially spend days, weeks, months to develop good behavioral models," Walter said. Wreal models are relatively fast to develop because they're less detailed. An important rule of thumb: "Model what you need, not what you can."

Microelectronics Journal, in-press, february 2011

Modeling of threshold voltage of a quadruple gate transistor

Md. Gaffar, Sayed Ashraf Mamuna, and Md. Abdul Matina

Available online 24 February 2011.
Abstract

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. Numerical simulation, self-consistent Schrodinger–Poisson equations, calibrated by 2D non equilibrium green function simulation, are used.

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SPICE Circuit Simulator Named IEEE Milestone

Simulating a circuit with SPICE is the industry-wide standard way to verify operation at the transistor level before manufacturing an IC. The program has become so ubiquitous that engineers often say they are going to “SPICE a circuit” when they are about to test one. To mark the 40th anniversary of SPICE—the Simulation Program with Integrated Circuit Emphasis—IEEE has designated its creation an IEEE Milestone in Electrical Engineering and Computing.

SPICE was made publicly available in 1971 so that chip designers could modify it—an early example of open-source software. Two years later, SPICE became well known after it was described in a paper by Pederson at the 16th Midwest Symposium on Circuit Theory, in Waterloo, Ont., Canada. During the next few years, developers around the world began using and modifying SPICE, leading it to become the industry standard it is today. “What happened was truly phenomenal,” Nagel wrote in “The Origins of SPICE.” “Within a few years, SPICE had achieved acceptance at almost all electrical engineering schools [for use in teaching] and had [spawned] a cottage industry to supply SPICE derivatives to the rapidly expanding integrated circuit industry.”

[Read more by Anna Bogdanowicz @ IEEE]

Papers in SSE (vol 57 , issue 1, March 2011)

Analytical threshold voltage model for lightly doped short-channel tri-gate MOSFETs

A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, N. Collaert, G. Pananakakis


Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET

Adelmo Ortiz-Conde, Francisco J. García-Sánchez

Research highlights

► Single completely generic equation of channel potential for undoped asymmetric independently driven double-gate MOSFETs. ► Channel potential equation is based on complex variables and is valid for all values of front and back-gate bias. ► The unified nature of the proposed equation provides a better basis for global physical insight. ► Several examples, including the all important fully symmetric case, are analyzed.


 Compact modeling of CMOS transistors under variable uniaxial stress

Nicoleta Wacker, Harald Richter, Mahadi-Ul Hassan, Horst Rempp, Joachim N. Burghartz

Research highlights

► We propose a method to simulate the effect of uniaxial stress on MOSFETs. ► The method is valid for any drain current and stress directions in (001) Si plane. ► It can perform static and dynamic simulations, in linear and saturation regions. ► It is simulator-independent and does not depend on the source of uniaxial stress. ► It is adaptable to other bulk CMOS nodes and to other technologies such as SOI.


 A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

F. Lime, R. Ritzenthaler, M. Ricoma, F. Martinez, F. Pascal, E. Miranda, O. Faynot, B. Iñiguez

Research highlights

► Valid for long-channel undoped ADGMOSFETS with independent gate operation. ► Fully analytical and explicit derivation with no iterative solutions. ► Accessible front and back gate charges, potentials and currents. ► Unification of symmetric and asymmetric cases. ► Physical solutions similar to classical MOS theory.


In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation

B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet

Research highlights

► We performed 2D simulations of germanium-on-insulator fully-depleted pMOSFET. ► Interface traps, mobility and leakage were calibrated versus experimental data. ► The prediction of electrical characteristics is accurate for several gate lengths. ► These simulations help in finding guidelines for improving the on-state current.


 Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces   

G. Hamaide, F. Allibert, F. Andrieu, K. Romanjek, S. Cristoloveanu

Research highlights

► Biasing the back interface in accumulation while extracting carrier mobility in FD-SOI MOSFETs leads to underestimated values. ► Apparent mobility degradation with decreasing film thickness in ultra-thin SOI MOSFET or Pseudo-MOSFET measurement is due to an additional component of the vertical electric field. ► In Pseudo-MOSFET measurements, the additional component of the vertical electric field comes from the traps and charges at the free-surface of the sample. ► We propose a new model to take this additional component of the vertical electric field into account.