IEEE SCV EDS: LDMOS reminder & upcoming

Sept. 14th
LDMOS - Technology and Applications
Shekar Mallikarjunaswamy, Alpha Omega Semiconductor

Sept. 28th
The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley
David Brock, Cristophe Lecuyer

Oct. 12th
Is it the End of the Road for Silicon in Power Management?
Dr. Alex Lidow, CEO Efficient Power Conversion Corporation

Details on IEEE SCV EDS website: http://www.ewh.ieee.org/r6/scv/eds

OLED simulation software

I'm copying here the press release (it must be takes as such, cum grano salis)

sim4tec announces the release of new version 3.0 of its OLED simulation software SimOLED.
New features include:

• Enhanced powerful graphical representation of results - line and contour plots
• Electronic, excitonic and optic module seamlessly combined
• Faster calculation speed
• Additional results for current, power, quantum efficiencies, CIE diagram and many more
• Updated graphical user interface

A special highlight is the combination of our well-proven and reliable electronic module with the excitonic and optic modules. This allows users to simulate voltage-dependent optical quantities like the colour maintenance of white OLEDs.
The software is ideally suited for conducting basic research, arbitrary OLED stack design, material parameter extraction and process window identification. Included in the software is an in-depth tutorial containing more than 20 examples, ranging from simple single layer devices up to white hybrid OLEDs.

IDESA Training Courses Calendar

Implementation of widespread IC DEsign Skills in advanced deep submicron technologies at European Academia.

Advanced Analog Implementation flow	Analog circuit design simulation and layout for 90nm and below.
Advanced Digital Physical Implementation flow	Power Aware physical design techniques, timing and power closure.
Advanced RF Implementation flow	RF Implementation Flow in deep sub-micron CMOS technology.
Design for Manufacturing flow	DFM issues are becoming increasingly important for 90nm and below.

The IDESA Course Booking System is managed and maintained by STFC Rutherford Appleton Laboratory, UK. If you have a booking enquiry, please email: idesa@stfc.ac.uk

	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
IDESA Course Calendar 2010
Advanced Analog Implementation flow									RAL
Advanced Digital Physical Implementation flow									AGH			LUND
Advanced RF Implementation flow											IMEC	PPAZ
Design for Manufacturing flow											ERLN
IDESA Course Calendar 2011
Advanced Digital Physical Implementation flow		ERLN
Design for Manufacturing flow		TUL				MONS

Course Location key:
AGH	AGH University of Science and Technology, Poland	CIME	CIME, France
ERLN	Fraunhofer IIS, Erlangen, Germany	IMEC	Interuniversitair Micro-Electronica Centrum, Belgium
LUND	University of Lund, Sweden	MONS	Université de Mons, Belgium
MONT	University Montpellier 2, France	NAP	Università degli Studi di Napoli Federico II
PPAZ	Péter Pázmány Catholic University, Hungary	RAL	Rutherford Appleton Laboratory, UK
STU	Slovak University of Technology in Bratislava, Slovakia	TUL	Technical University of Lodz, Poland

Where to study nanotech?

Marie Curie Fellows - Centro de Química da Madeira, Funchal, Madeira Island, Portugal.

Job Reference: CQM-WIIP-2010

Where to study nanotech in India?

Nanotechnology in USA

Visit also Nanotechnology - TINC

Accelicon announces Context Dependent Modeling Platform

I copy a part of the original post:

Accelicon Technologies, Inc. announces the market’s first commercially available Context Dependent Modeling Platform based on Accelicon’s flagship device modeling solution MBP. The performance of FETs can vary significantly, at advanced process nodes, due to layout dependent proximity effects. Sources of LDEs include Well Proximity Effect (WPE), lithography distortions, un-intentional stress sources such as Shallow Trench Isolation (LOD Effect) and intentional stressors which are used to enhance the performance of the device. These enhancement techniques include dual-stress liners, embedded SiGe and stress memorization techniques. At advanced process nodes engineers must analyze LDEs to minimize undesirable proximity effects and lithography distortions, and effectively utilize stress enhancement techniques. This analysis can only be conducted after layout extraction, SPICE modeling alone is not sufficient. 

Read more at the original post in LinkedIn:

Accelicon announces Context Dependent Modeling Platform