Simulating the Memristor with spice (as of September 2010)

Here you have a list of papers where people model a memristor:


- H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.

- Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.

- D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.

- "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

- Valsa, J., Biolek, D. and Biolek, Z. , "An analogue model of the memristor". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, n/a. doi: 10.1002/jnm.786

Lot of work, isn't it?

www.SoCconference.com

8th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Date: Nov. 3-4, 2010
Venue: Hilton Irvine/Orange County Airport
Agenda & Schedule

Early Bird Registration Is Now Open!

Three distinguished keynote speakers:

1. Dr. Ivo Bolsens, Senior Vice President and CCEO, Xilinx Inc.

2. Dr. J. Antonio Carballo, WW Manager, IBM Microelectronics Services, Semiconductor Partner, IBM VC Group, IBM.

3. Raouf Y. Halim, CEO, Mindspeed Technologies, Inc.

New record set for ferroelectric data storage

Scanning Nonlinear Dielectric Microscope: inset left: Shows topography and electric dipole-moment; inset right: Example of a ferroelectric information storage; [Read more...]

HP and Hynix - Bringing the memristor to market in next-generation memory

Today, HP announced a joint development agreement with Hynix Semiconductor Inc., to develop a new kind of computer memory – one that will employ memristor technology pioneered by researchers at HP Labs.

LDMOS - Technology and Applications

Speaker: Shekar Mallikarjunaswamy, Alpha Omega Semiconductor
Date: Sept 14th, 2010
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara , CA 95051 .

Abstract: A key device that is used in most high voltage (20 to 120V) power integrated circuits for power management applications is the Lateral Diffused MOS (LDMOS) transistor. Recent interest in ‘green” products have further increased the demand for integrated HV LDMOS devices in CMOS and BCD technologies to build higher efficiency dc-dc converters for consumer and LED markets. This presentation will journey through the structural innovations from “planar” to “trench” and to state-of-the-art “RESURF” LDMOS devices in both junction and dielectric isolation technologies for the past two decades. The physics of operation, figure of merits used for device comparison, layout techniques including integration of LDMOS into modern CMOS/BCD technologies will be discussed. Device and process simulations to optimize device parameters including SPICE macro circuits to model “quasi-saturation” and “Cgd” capacitance will be described. Methods to improve hot carrier reliability and ESD robustness of LDMOS devices will be highlighted. Finally, LDMOS circuit topologies and their applications in consumer, computer and telecommunication products will be presented to let the audience comprehend and appreciate the significance of LDMOS devices to modern power management products.

Web link: http://www.ewh.ieee.org/r6/scv/eds/