IBM INDIA: Job Opportunities

IBM INDIA SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER(SRDC)

IBM SRDC develops all of IBM’s semiconductor technologies including SOI, Bulk CMOS, RFCMOS, HV CMOS, and SiGe HBT BiCMOS Technologies. The IBM SRDC at Bangalore is responsible for developing compact models and process design kits (PDK), leading edge computational lithography, functional characterization support and theory, designs, models for nanoscale devices.

Job Opportunities

COMPACT MODELING ENGINEER: Work in a very challenging environment with experienced device modelers and RF circuit designers. The responsibilities will include development of compact models for both active (FET, BJT) and passive (diodes, varactors, MIMCAP, inductors) devices in mixed signal, and RF technologies. Working closely with device engineers to define parameter targets and with foundry clients to resolve any modeling issues in design. Defining test programs for DC and RF device measurement and characterization. Use of software such as ICCAP to extract parameters for BSIM, PSP or other models. Strong semiconductor device physics background and previous experience of device modeling / characterization / design are required. The candidate should have a MS degree in Electrical Engineering / Physics with at least 3 years of experience in device modeling related work or a PhD degree in Electrical Engineering.

DESIGN AUTOMATION TECHNICAL LEAD: An experienced professional to lead the PDK Design Automation (DA) team. Bangalore team is responsible for device model and enablement for process development kit (PDK) for some of the key technologies of IBM's specialty foundry business. The person leading the DA team will be part of a highly talented team with global experience and should be able to maintain the best-in-class PDK quality that IBM is known for. The minimum experience for this position should be at least 6-7 years of industry experience in the area of Design Automation (Parasitic extraction, Final kit Testing, DRC code generation, Pcell development) in the RF, analog & mixed signal environment. The ideal candidate should be able to lead a team of 10+ engineers, technically mentor and guide on project deliverables, can effectively collaborate with different GEO's like US & France and interface with Foundry customers on Design Automation related issues. Minimum academic qualification should be Master's with 6-7 years or PhD with 3+ years of relevant experience. Exceptional candidates with outstanding credentials with Bachelor's degree with 8-9 years of experience may also be considered. Previous management experience is a plus.

For more details visit website : www.ibm.com
Send resume to anibandy@in.ibm.com

Job offers in LinkedIn

Remember: this is only a copy of a post in LinkedIn. We're not associated in any way to any of them...

Senior Research & Development Engineer
Group: Silicon Engineering Group
Location: Hyderabad, India
Contact @ akshat.kumar@synopsys.com

This position is for a senior R&D engineer who will join the TCAD team and work on the development and maintenance of state of the art back-end/interconnect analysis tools. Primary responsibilities include designing and developing physical models and numerical algorithms and implementing these algorithms in general purpose multidimensional semiconductor back-end/interconnect simulators in C++.
- PhD in a relevant field.
- Exp. with semiconductor back-end/ interconnect simulation tools focusing on one or, more of electrical, thermal, mechanical, and reliability analysis, numerical methods for solving partial differential equations (finite element and/or finite volume method), mesh generation.
- ~3 to 5 years of experience as a developer on large Finite Element Analysis simulators in either a commercial, or industrial/research lab setting. Prior experience with Synopsys TCAD tools is strongly preferred.
-Software development experience in C++ and preferably Tcl/Tk.
-Good communication skills and the ability to work within a team are essential.

some reading for summertime

Appl. Phys. Lett. 96, 253301 (2010); doi:10.1063/1.3453661 (3 pages)

Current bistability and carrier transport mechanisms of organic bistable devices based on hybrid Ag nanoparticle-polymethyl methacrylate polymer nanocomposites

Won Tae Kim, Jae Hun Jung, Tae Whan Kim, and Dong Ick Son

Abstract:The current bistability and the carrier transport mechanisms of organic bistable devices (OBDs) using Ag nanoparticle-polymethyl methacrylate (PMMA) nanocomposites have been investigated. Current-voltage measurements at 300 K on the Al/Ag nanoparticles embedded in the PMMA layer/indium-tin-oxide devices exhibit a current bistability with an ON/OFF ratio of 10³. Write-read-erase-read sequence results demonstrate the switching characteristics of the OBD. The cycling endurance number of the ON/OFF switching for the OBD is above 7×10⁴. The current bistability and carrier transport mechanisms of the OBD fabricated utilizing hybrid Ag nanoparticle-PMMA polymer nanocomposites are described on the basis of the experimental data.

 Physica E: Low-dimensional Systems and Nanostructures

Quantum transport modeling of defected graphene nanoribbons 

 I. Deretzis, G. Fiori, G. Iannaccone, G. Piccitto and A. La Magna


Abstract: We study backscattering phenomena during conduction for graphene nanoribbons of μm lengths, from single vacancy scatterers up to finite defect concentrations. Using ab initio calibrated Hamiltonian models we highlight the importance of confinement and geometry on the shaping of the local density of states around the defects that can lead to important alterations on the transport process, giving rise to impuritylike conduction gaps in the conductance distribution. Within a statistical analysis of finite defect concentration we show that conductance degradation can become very important.




 Solid-State Electronics
The spatial origin of current noise in semiconductor devices in the framework of semiclassical transport
C.E. Kormana, B.A. Noaman

Abstract: A new model to semiconductor device electronic noise is presented in the framework of semiclassical transport theory. The salient feature of this model is that it connects the current noise characteristics directly to the physics of scattering of the semiclassical transport theory and makes no additional assumption regarding the nature of noise. Employing this approach, this work investigates the spatial origin of the current noise across two semiconductor structures. In this approach the terminal current noise is directly related to carrier scattering inside the device, which is accounted for in the Boltzmann transport equation (BTE), without the need to add Langevin noise terms to the calculations. Accordingly, it utilizes the well-established spherical harmonics expansion (SHE) technique to solve the BTE, and it combines analytical and numerical methods, in contrast with the Monte Carlo (MC) approach that employs ensemble averages of randomly generated events. The model leads to the solution of a time-dependent transient solution of the BTE with special initial and Ohmic boundary conditions that is solved in the frequency domain to directly compute the terminal current noise spectral density. It is also shown that with this approach the Nyquist theorem under thermal equilibrium conditions is recovered.

 

The Ten Commandments for Effective Standards

The Ten Commandments for Effective Standards:

Practical Insights for Creating Technical Standards

Karen Bartleson (Author)

Publisher: Synopsys Press (May 7, 2010)
Language: English
ISBN-10: 1617300020
ISBN-13: 978-1617300028

About the Author:
Karen Bartleson has three decades' experience in the computer chip industry. She is known for her work in the area of standards for electronic design automation, and is also one of the pioneers into social media in her industry, including Twitter. She is the author of "The Standards Game," a blog focused on the standards arena. Karen holds a BSEE from California Polytechnic State University, San Luis Obispo, California, and was the recipient of the Marie R. Pistilli Women in Design Automation Achievement Award in 2002. Her Twitter handle is @karenbartleson. --This text refers to the Paperback edition.

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

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MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
   * Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
   * Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
   * Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
   * Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
   * David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
   * Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
   * Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
   * Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

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