Some papers (May 2010) I've found interesting...

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

5457978abstract

Bronckers, S.;   Van der Plas, G.;   Vandersteen, G.;   Rolain, Y.;  
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium 

This paper appears in: Instrumentation and Measurement, IEEE Transactions on
Issue Date: June 2010
Volume: 59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370 
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-$muhbox{m}$ triple-well common-source complementary metal–oxide–semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 $Omega$.

Thermal shot noise in top-gated single carbon nanotube field effect transistors

5464988abstract

Chaste, J.;   Pallecchi, E.;   Morfin, P.;   Feve, G.;   Kontos, T.;   Berroir, J.-M.;   Hakonen, P.;   Placais, B.;  
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889 
Date of Current Version: 13 May 2010

The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of

13 μe/

√  Hz

in the 0.2–0.8 GHz band. 

Dielectric constants of atomically thin silicon channels with double gate

Kageshima, Hiroyuki;   Fujiwara, Akira;  
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364 
Date of Current Version: 13 May 2010

Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.

 

Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques

Lehnhardt, M.;   Hamwi, S.;   Hoping, M.;   Reinker, J.;   Riedl, T.;   Kowalsky, W.;  
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416 
Date of Current Version: 13 May 2010

The charge carrier density of the p-type doped organic semiconductor 2,7-bis(9-carbazolyl)-9,9-spirobifluorene is determined for varied doping concentrations. As p-type dopant molybdenum trioxide is used. We determine the carrier density by measuring the polaron induced optical absorption and by a capacitance-voltage analysis. We show that both results are in excellent agreement. An almost linear dependence of the charge carrier density on the doping concentration is observed. Carrier densities on the order of 10¹⁸ cm^-3 at a dopant concentration of 1 mol % can be achieved. Overall, a low doping efficiency on the order of 2%–4.5% is evidenced.

The effect of traps on the performance of graphene field-effect transistors

Zhu, J.;   Jhaveri, R.;   Woo, J. C. S.;  
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785 
Date of Current Version: 13 May 2010

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.

 

Training Course on Compact Modeling: Registration Open

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona, Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

The lectures and topics of their lectures will be the following:


1. Tibor Grasser (TU-Wien, Austria) - Transport modeling

2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling

3. Jamal Deen (McMaster University, Canada) - Noise modeling

4. Benjamin Iñiguez (URV, Spain) - Analytical small-signal modeling

5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling

6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling

7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs

8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies

9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"

10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"

12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"

The final programme, with the timetable, is already available!

May 7, 1952: The Integrated Circuit …

1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com

Organic Transistor Could Outshine OLEDs

”The light-emitting transistor is a remarkably versatile device architecture,” says Alan Heeger, a physics professor at the University of California, Santa Barbara. Heeger’s lab developed an OLET inverter circuit earlier, but its quantum efficiency was much lower. He called the 5 percent external quantum efficiency ”remarkable,” because it suggests that nearly 100 percent of the carriers in the emissive layer are emitting photons. ”If that is indeed true,” Heeger says, ”they have made an important step forward.”

more at IEEE Spectrum

3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

Deadline for abstract submission has been extended:

- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels

Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat



This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.