9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University
9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN
10:00 Coffee break
10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI
11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL
11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester
12:00 Lunch
13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow
14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum
14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec
15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET
15:30 End of the Workshop
Jul 22, 2009
ESSCIRC/ESSDERC early registration deadline ***26/7/2009***
Some information from Matthias Bucher
Dear Colleagues,
Please let me draw your attention to the deadline for early registration for ESSDERC/ESSCIRC 2009 in Athens, 14-18/9/2009, is this Sunday, 26 July. For those who have not registered yet, consider the reduced registration fees, http://www.esscirc2009.org/?pid=3.
I also would like to draw your attention to the Tutorials on Monday 14/9/2009, http://www.esscirc2009.org/?pid=7. Of course you are aware the MOS-AK workshop is held on Friday 18/9/2009, please **do** register as well! (even though it is free, and even for those of you who might not attend ESSDERC/ESSCIRC).
As an additional information, I’m attaching below some links to hotels that you might want to consider booking, in the Acropolis and Plaka region, about 20-25 minutes (either metro and/or walking) or 15 minutes by taxi, from the Caravel hotel where the conference is held. Hotels very close to the Caravel are probably already booked (those indicated on the conference site) or very expensive (Hilton, and Caravel). Don't delay booking, I hope these are of some help.
Acropolis Museum Boutique hotel, 48 Sygrou Ave., 11720 Athens
http://www.booking.com/hotel/gr/acropolis-museum-boutique.en.html?sid=86c27c055ff3d2b31320a517ff769305
Airotel Parthenon, 6 Makri Str., 11742 Athens
http://www.booking.com/hotel/gr/parthenon.en.html?sid=86c27c055ff3d2b31320a517ff769305
Acropolis Select Hotel, 37-39 Falirou Str., 11742 Athens
http://www.tripadvisor.com/Hotel_Review-g189400-d230390-Reviews-Acropolis_Select_Hotel-Athens_Attica.html
or hotels in the "Plaka" area (again close to Acropolis and close to metro stations)
Amazon Hotel, Mitropoleos 19 & Pentelis 7, 10557 Athens
http://www.booking.com/hotel/gr/amazonathens.html
PLAKA HOTEL ATHENS, 7 Kapnikareas & Mitropoleos, Athens
http://www.holiday-in-athens.com/athens/plaka-hotel-athens.html
Jul 17, 2009
Post-Silicon Solutions Emerging
Post-Silicon Solutions Emerging:
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West. High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS.
David Lammers, News Editor -- Semiconductor International, 7/15/2009
Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West.
 |
| "We need disruptive materials and technologies," said Raj Jammy of Sematech. |
High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS. Jammy, in charge of materials and emerging technologies research at Sematech, warned that "people entrenched in the silicon world" may need to rethink as scaling of today's CMOS transistors becomes increasingly difficult.
"We need disruptive materials and technologies," Jammy said, describing R&D progress on several post-22 nm options. Progress is being made on heterogeneous devices, where germanium is used as the channel in the pFET and indium gallium arsenide (InGaAs), for example, on the nFET. Nanowires with a gate-all-around design are drawing more R&D attention, and work continues on finFETs -- vertical structures that allow better control of the channel.
Memory R&D is equally vibrant. For decades, mainstream memories have been based on charge storage. "But when you make these devices really small, charge storage is no longer possible." On the horizon are phase change memories (PCRAMs) and metallic resistive RAMs (ReRAMs), though Jammy acknowledged that the question regarding ReRAM technology is: "Does it work at less than 20 nm?"
Also under study are zero-leakage nanoelectrical-mechanical system (NEMS) devices, which Jammy said "exhibit instant on and off." And because they are mechanical, they can safely operate in hazardous environments, such as a nuclear power plant.
 |
| Schubert Chu of Applied Materials spoke of the potential of carbon-doped silicon for nFET strain. |
Schubert Chu, an Applied Materials product manager for epi/LPCVD products, examined the possibility of embedded silicon carbon (eSiC) being used to enhance the performance of the nFET. While embedded silicon germanium (eSiGe) has served to effectively strain the pFET, SiC has been a tougher challenge, largely because the carbon atoms tend to move around.
Chu said that an AMD-led team has shown a 30% improvement with nFETs strained by SiC structures. "Silicon carbon is on track to be adopted at the 22 nm generation."
SiGe stressors face challenges as the germanium content moves from 25-30% at the 45 nm node to >40% at the 22 nm node. Applied Materials has developed a "Siconi" pre-clean option for its Centura epitaxial deposition tool, which Chu said will extend epi strain technologies.
Jammy said the industry faces serious cost challenges. "When we hear that it may cost $80M for a EUV scanner, we are not going in the right direction on costs," he said.Organic semiconductor researchers honoured by Institute of Physics
From the OSADirect Newsleter:
The 2009 Faraday Medal, one of the Institute's three gold medals, has been awarded to Professor Donal Bradley FRS for his pioneering work in the field of plastic electronics. Professor Bradley who holds the Lee Lucas Chair in Experimental Physics, is Director of the newly established Centre for Plastic Electronics at Imperial.
Professor Bradley's research focuses on optimising plastic semiconductors for use in a wide range of electronic devices, with applications spanning displays, lighting, electronics, solar energy, communications and medical diagnostics.
Professor Bradley said, "What a wonderful way to celebrate the twentieth anniversary of conjugated polymer LEDs - a discovery that helped to launch plastic electronics on the path to its present day vibrancy as an academic research field with great commercial potential. I am delighted to have been able to walk that path in the company of so many talented students, postdoctoral researchers and academic and industrial colleagues – this award recognises the fruits of a great many, very enjoyable collaborative interactions."
Professor Jenny Nelson has been awarded the Joule Medal. Prof. Nelson is currently working on the use of molecular or 'plastic' electronic materials in solar cells, in order to reduce the cost of solar electricity. Once the basic properties of the materials are properly understood, design rules can be developed for new materials and types of device with better performance.
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