QUCS developments

The QUCS development team is taking part in the MOS Modelling and Extraction Working Group (MOS-AK) Verilog-A standardisation initiative.

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The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)

Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"

Future Solutions of System On Chip (SoC)

Frédéric Boeuf, Principal Engineer at STM, gave a short course at the VLSI Symposium 2009 in Kyoto. It is a synthesis on the silicon technology uses for system on chip applications, and some prospect about the future solutions.

View the slide presentation...

IMEC Tips 10 nm Options at Tech Forum

I copy a post from Semiconductor International:
IMEC Tips 10 nm Options at Tech Forum: "At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time..."
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MNE'09 in Ghent

The 35th International Conference on Micro & Nano Engineering (MNE), to be held in Ghent, Belgium from 28 September to 1 October 2009.

The scope is about micro- and nano-fabrication and manufacturing using lithography and other nano-patterning related approaches. The conference brings together engineers and scientists from all over the world to discuss recent progress and future trends in the fabrication, manufacturing and application of micro-and nano-structures and devices. Applications in electronics, electromechanics, environment and life sciences are discussed such as: nanoelectronics, MEMS-NEMS, bioMEMS and lab-on-a-chip devices.

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International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.

This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for Abstract Submission is July 15 2009.

Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk

If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is August 15, 2009.

This is the only workshop especifically devoted to the compact modeling of TFT!