Aug 29, 2019

#Microsoft readies #exFAT patents for #Linux and #opensource | ZDNet https://t.co/nGURHD35IU https://t.co/NWBfJOiOyL


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August 29, 2019 at 11:11AM
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Aug 28, 2019

#IBM’s #OpenSource POWER Play: A #RISC-V Business? https://t.co/11lFmDgnpU https://t.co/io81PcbNqh


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August 28, 2019 at 04:11PM
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F. Ávila Herrera et al., "Advanced Short-Channel-Effect Modeling With Applicability to Device Optimization—Potentials and Scaling," in IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3726-3733, Sept. 2019 https://t.co/6vkIpdH9F6 #paper https://t.co/sVWISPjNKN


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August 28, 2019 at 05:14PM
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Aug 27, 2019

3rd International Workshop on MEMS and Sensor System 2019 (#IWMS 2019) Aug. 27-29 Hi Chi Minh City (VN) https://t.co/hOnegKRO5E #paper https://t.co/fPmyokXQ5w


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August 27, 2019 at 05:11PM
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Is the Threat of ‘Fake Science’ Real? "Thinking ahead to the potential for fake science can better equip research institutions to respond to targeted disinformation while preserving an open scientific community." https://t.co/nzAokiqybW #paper https://t.co/D0WasFZRwv


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August 27, 2019 at 02:31PM
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Y. Yamamoto et al., "The Study of Plasma Induced Damage on 65-nm Silicon on Thin BOX Transistor," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 825-828, 2019 https://t.co/ppz92LZnNi #paper https://t.co/7hmMCY5rvx


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August 27, 2019 at 11:58AM
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B. K. Esfeh, V. Kilchytska, N. Planes, M. Haond, D. Flandre and J. Raskin, "28-nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements Extraction at Cryogenic Temperature Down to 77 K," in IEEE JEDS, vol. 7, pp. 810-816, 2019. https://t.co/VXOuHjBAWI #paper https://t.co/mT1vV0psze


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August 27, 2019 at 09:54AM
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低频噪声测试在新兴半导体材料和器件物理机制探索的应用研究 Application Research of Low Frequency Noise Testing in the Exploration of Emerging Semiconductor Materials and Devices Physical Mechanism https://t.co/Y9lDjd1kPn #paper https://t.co/6X4218ejOF


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August 27, 2019 at 09:15AM
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Aug 26, 2019

V. Veliadis, "The Impact of Education in Accelerating Commercialization of Wide-Bandgap Power Electronics [Expert View]," in IEEE Power Electronics Magazine, vol. 6, no. 2, pp. 62-66, June 2019 doi: 10.1109/MPEL.2019.2910715 https://t.co/R14V6BDxXR #paper https://t.co/NnTfIqzaRR


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August 26, 2019 at 08:45PM
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IEEE Annual Election: IEEE President-Elect Candidate: DEJAN S. MILOJICIC, PhD https://t.co/YGXMj7XzQM (Nominated by IEEE Board of Directors) Distinguished Technologist; Hewlett Packard Labs Palo Alto, California, USA https://t.co/eCpVS4yzu9 #paper https://t.co/4b8EOTaQMF


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August 26, 2019 at 05:36PM
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B. Contreras, G. Ducoudray, R. Palomera and C. Bernal, "Automated Parameter Extraction and #SPICE #Model Modification For Gate Enclosed MOSFETs Simulation," 16th SMACD, Lausanne, Switzerland, 2019, pp. 189-192 https://t.co/nBleBsXkFf


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August 26, 2019 at 03:09PM
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Aug 23, 2019

The EPFL HEMT Model is a design-oriented charge-based model for dc operation of AlGaAs/GaAs and AlGaN/GaN-based high-mobility field-effect transistors. https://t.co/KoxvcDSPTh https://t.co/c5fUa76rV7 #paper https://t.co/k5U7l3htU6


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August 23, 2019 at 03:50PM
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#Welsh put £1.3m into #compound process #technology development https://t.co/Jhdwm4WDM8 #paper https://t.co/hmOlw93jdl


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August 23, 2019 at 03:50PM
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“IEEE EDS MQ at IIT Kanpur: B.Iniguez, URV, Spain: Universal TFT compact model A.Kottantharayil, IIT Bombay: Graphene based devices A.Dixit, IIT Delhi: Multiple Gate FET Modeling Y.Chauhan, IIT Kanpur: Negative Capacitance Transistor https://t.co/bbY1s1g62H #paper


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August 23, 2019 at 03:50PM
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#Compact #Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model https://t.co/KP3af6KD3E https://t.co/hDA7MDEVnc


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August 23, 2019 at 03:50PM
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Aug 22, 2019

For the #SourceForge August 2019 “Staff Pick” Project of the Month, we selected #Octave Forge, a collection of packages providing extra functionality for #GNU Octave which is a great alternative to MatLab https://t.co/P6SMMrg2nM #paper https://t.co/ujqlq3mfWr


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August 22, 2019 at 09:38AM
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Aug 21, 2019

Engineers make #transistors and electronic devices entirely from #thread https://t.co/Q9QQ7ZZLPs #paper https://t.co/9U75LzDWVT


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August 21, 2019 at 09:08PM
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Aug 19, 2019

Maciej Ogorzałek Candidate for 2020 IEEE Vice President-Elect for Technical Activities


To learn more about my qualifications, IEEE activities and accomplishments, please visit
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Aug 16, 2019

Newly discovered properties in the compound uranium ditelluride, or UTe2, show that it could prove highly resistant to one of the nemeses of #quantum #computer development https://t.co/Lul2Op5W6R #paper https://t.co/C1Nz7Cj5TF


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August 16, 2019 at 09:55AM
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Aug 15, 2019

Why Los Angeles #LA decided to #opensource its future https://t.co/1HsXedylg5 https://t.co/KYyrpOgqWo


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August 15, 2019 at 08:11PM
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Aug 14, 2019

Flexible Design Pursues PDK, Power; Battery startups aim to enable #flexible #electronics https://t.co/iVc4Wzr78i #paper https://t.co/Pt78L534lg


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August 14, 2019 at 04:53PM
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Aug 13, 2019

#Huawei to help create nation's first #opensource #foundation https://t.co/OGplZqOI1S https://t.co/Xsdh3Zva8y


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August 13, 2019 at 09:43AM
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Aug 12, 2019

[papers] Compact Modeling

Q. C. Nguyen, P. Tounsi, J. Fradin and J. Reynes, "Development of SiC MOSFET Electrical Model and Experimental Validation: Improvement and Reduction of Parameter Number," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 298-301.
doi: 10.23919/MIXDES.2019.8787050
Abstract: In this work, a new approach for electrical modeling of Silicon Carbide (SiC) MOSFET is presented. The developed model is inspired from the Curtice model which is using a mathematic function reflecting MOSFET output characteristics. The first simulation results showed good agreement with measurements. Improvement is needed in order to increase model accuracy and to take into account the influence of the junction temperature on device characteristics.

D. Kasprowicz, "Semiconductor Device Parameter Extraction Based on I–V Measurements and Simulation," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 321-326.
doi: 10.23919/MIXDES.2019.8787195
Abstract: The paper presents a method for extracting the physical parameters of a semiconductor device based on the measurements of its electrical response (e.g. transfer characteristics) combined with simulation. Such extraction is usually performed by an optimization algorithm seeking device-parameter values that minimize the difference between the measured response and its simulated equivalent. The proposed approach needs only an average of 13 objective-function evaluations, i.e. device simulations, to extract three parameters of a single device. If the parameters of a group of devices of the same type are to be extracted, the average number of simulations drops to four per device. This number is much smaller than in conventional optimization procedures. Thus, the proposed procedure can be used even in the absence of an accurate compact model, when time-consuming TCAD simulation must be used to determine the device’s response.

D. Tomaszewski, J. Malesińska, G. Głuszko and K. Kucharski, "Current vs Substrate Bias Characteristics of MOSFETs as a Tool for Parameter Extraction," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 87-91.
doi: 10.23919/MIXDES.2019.8787068
Abstract: An application of the drain current vs substrate bias characteristics of MOSFETs for the device parameter extraction is presented. Modeling of the substrate bias effect on the MOSFET drain current is briefly discussed. A method of the MOSFET characterization is formulated. It requires a measurement of two I(V) characteristics, including the ID(VBS) smooth curve measured in a "sweep" mode. The method allows to extract the threshold voltage parameters and to estimate the in-depth doping profile in the substrate. The proposed approach is demonstrated using I(V) data of the MOSFETs manufactured in ITE in a bulk CMOS process.
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#Huawei announces #opensource Harmony OS https://t.co/3oBWFgcXVc https://t.co/kxN86XBMyO


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August 12, 2019 at 11:22AM
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Aug 1, 2019

Horizon Europe - Commission announces top experts to shape Horizon Europe (2021-2027) missions https://t.co/5s7twEGfG4 #paper https://t.co/YPw6s3cUqX


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August 01, 2019 at 12:18PM
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Jul 30, 2019

[mos-ak] Joint ESSDERC/ESSCIRC Tutorial in Krakow (PL) on Sept.23, 2019

Joint ESSDERC/ESSCIRC Tutorial: 
Nanoscale Technology – Transistor Modeling – IC Design 
Auditorium Maximum, the Jagiellonian University
Krakow (PL) on Sept.23, 2019

Together with local organization team, MOS-AK Association invites you to Joint ESSDERC/ESSCIRC Tutorial: Nanoscale Technology – Transistor Modeling – IC Design which will be organized at Auditorium Maximum of the Jagiellonian University in Krakow (PL) on Sept.23, 2019

Our joint ESSDERC/ESSCIRC Tutorial aims to provide in-depth coverage of highly relevant R&D topics by world-class experts. We will discuss and present the frontiers of electron device modeling with emphasis on the complete UT SOI development chain, reviewing the nanoscale level technologies, devices TCAD numerical simulations, thru its simulation-aware compact/SPICE modeling up to selected topics of the transistor level IC design for advanced applications. This joint tutorial is designed for academic researchers, device process engineers who are interested in device modeling; academic/industrial ICs designers (to explore RF/Analog/Mixed-Signal) and those starting in these areas as well as device fabrication, electrical characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC fabrication and its simulation in using modern SPICE/Verilog-A device models (tutorial agenda listed below).

Joint ESSDERC/ESSCIRC Tutorial will be followed (Sept. 24-26, 2019) by four TRACK4: "'Compact Modeling of Devices and Circuits" Sessions with invited talk "The Synergy SPICE – Compact Models" by Prof. Andrei Vladimirescu and 11 regular conference papers (see all the details below)

Tutorial Agenda: 
8:00 – 8:30 – Registration
8:30 – 9:15 – Technology: Guillaume Besnard, SOITEC (F) – UT SOI Processing and Device Fabrication
9:15 – 10:00 – Technology: Ahmed Nejim, Silvaco Inc. (USA) – UT SOI TCAD Numerical Process/Device Simulation
10:00 – 10:30 – Coffee break
10:30 – 11:15 – Devices: Thierry Poiroux, CEA–Leti (F) – Compact modeling for FDSOI technologies: Main challenges and possible solutions
11:15 – 12:00 – Devices: Roberto Murphy, INAOE (MX) – RF Electrical Characterization
12:30 – 14:00 – Lunch
14:00 – 14:45 – Design: Christian Enz, EPFL (CH) – Systematic Design of Low-power Analog/RF CMOS Circuits using the Inversion Coefficient
14:45 -15:30 – Design: Humberto Andrade da Fonseca (Cadence, US) – Advanced SOI Design and Reliability/Ageing Simulations
15:30 – 16:00 – Coffee break
16:00 – 17:00 – Panel discussion
Venue:
Auditorium Maximum, the conference center of the Jagiellonian University
ul. Krupnicza 33, 
31-123 Kraków (PL)
Online registrations will be accepted until 20 August 2019.  
https://esscirc-essderc2019.org/how-to-register/  

On the behalf of the local organization team
Wladek Grabiński (GMC, CH)
Daniel Tomaszewski (ITE, PL)
ESSDERC/ESSCIRC
TRACK4: Compact Modeling of Devices and Circuits
https://esscirc-essderc2019.org/program/
Tuesday September 24, 2019 (14:00-15:20)

IdTimePaper Title/Location/Session
5189 14:00 -
14:26		Cryogenic MOSFET Threshold Voltage Model
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
5246 14:26 -
14:53		Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
5216 14:53 -
15:20		Test Chip for Identifying Spice-Parameters of Cryogenic BiFET Circuits
Location: Seminar room
Session: Compact Modeling Under Cryogenic Conditions 
Wednesday September 25, 2019 (10:20-12:00)
IdTimePaper Title/Location/Session
5226 10:20 -
10:53		First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices
5253 10:53 -
11:26		Impact of SiGe HBT Hot-Carrier Degradation on the Broadband Amplifier Output Supply Current
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices 
5180 11:26 -
12:00		Monolithically Integrated GaN Power ICs Designed Using the MIT Virtual Source GaNFET (MVSG) Compact Model for Enhancement-Mode p-GaN Gate Power HEMTs, Logic Transistors and Resistors
Location: Seminar room
Session: Modeling of Compound Semiconductor Devices 
Wednesday September 25, 2019 (14:20-15:40)
IdTimePaper Title/Location/Session
5363 14:20 -
14:46		The Synergy SPICE – Compact Models
Location: Seminar room
Session: Advances in MOSFET Modeling 
5141 14:46 -
15:13		Comparison of Modeling Approaches for Transistor Degradation: Model Card Adaptations Vs Subcircuits
Location: Seminar room
Session: Advances in MOSFET Modeling 
5316 15:13 -
15:40		FOSS EKV2.6 Verilog-A Compact MOSFET Model
Location: Seminar room
Session: Advances in MOSFET Modeling 
Thursday September 26, 2019 (10:20-12:00)
IdTimePaper Title/Location/Session
5251 10:20 -
10:53		Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
5329 10:53 -
11:26		Compact Modeling of Low Frequency Noise and Thermal Noise in Junction Field Effect Transistors
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
5239 11:26 -
12:00		Evaluation of Static/Transient Performance of TFET Inverter Regarding Device Parameters Using a Compact Model
Location: Medium Aula A
Session: Modeling of Trap Effects and Noise 
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Jul 23, 2019

#IEEE Update of the International Roadmap for Devices and Systems (#IRDS) Sets Course for Computer and Electronics Industry Growth https://t.co/WwvxXl4Sq8 #paper https://t.co/ZOwLjWV0Sr


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July 23, 2019 at 05:31PM
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Looking for #Quality in #TCAD-Based Papers #IEEE #TED: “What is the definition of high quality?” In this editorial, at least partially, this question is addressed. https://t.co/c1G0YXgIdD #paper https://t.co/MbhLzUa4AZ


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July 23, 2019 at 02:11PM
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#IBM gives #cancer_killing drug AI project to the #OpenSource community | ZDNet https://t.co/GdgoUmx5UT https://t.co/lfC2v7MuFP


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July 23, 2019 at 11:34AM
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CODEOCEAN: Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs

CODEOCEAN capsule written in OCTAVE which calculates the current and transconductances (gm, gmd and gms) using the charge based approach introduced in [1]. The capsule generates graphs demonstrating model versus TCAD simulations. The user can use the capsule code to experiment and reproduce the results in the paper [1]. 
The capsule is provided at the IEEE explorer site under the "Code&Datasets" link. https://ieeexplore.ieee.org/document/8371530 / doi: 10.1109/TED.2018.2838101 
Or at the link below https://codeocean.com/capsule/8244803/tree"

FIG: IdVg and gmVg at Vd=10mV
REF:
[1] N. Makris, F. Jazaeri, J. Sallese, R. K. Sharma and M. Bucher, "Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances," in IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2744-2750, July 2018.
doi: 10.1109/TED.2018.2838101
Abstract: The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
Keywords: junction gate field effect transistors;semiconductor device models;mobile charges;double-gate junction field-effect transistor;classical electron device;low-noise applications;power electronics;long-channel symmetric double-gate junction FET;symmetric DG JFET;charge-based modeling;physics-based compact models;drain current;Electric potential;JFETs;Logic gates;Integrated circuit modeling;Junctions;Mathematical model;MOSFET;Analytical model;circuit simulation;compact model;junction field-effect transistor (JFET);temperature effect



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[paper] A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

1
Department of Electrical and Electronic Teaching, 
College of Information Science and Engineering, 
Huaqiao University, Xiamen 361021, China

2
Department of Electronic Engineering, Jinan University, Guangzhou 510632, China
*
Correspondence: yufei_jnu@126.com; Tel.: +86-0592-6162-385
†
These two authors contributed equally to this work.

Received: 10 May 2019 / Accepted: 12 June 2019 / Published: 14 July 2019
Electronics 2019, 8(7), 785; https://doi.org/10.3390/electronics8070785

Abstract

: 
A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal’s experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10−7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal’s experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.

Keywords:
 silicon-on-insulator MOSFETs; surface potential; back-channel potential; full-depletion; analytical I-V model
Electronics 08 00785 g001 550
Figure 1. x-y cross section of silicon-on-insulator (SOI) MOSFETs.
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Jul 15, 2019

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation - #Empyrean #Semiwiki https://t.co/JP9u2Tv6Be #paper https://t.co/bY6kqzdFZf


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July 15, 2019 at 11:57AM
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