IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation

The first IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation will be held in the Moller Center, in Cambridge, UK, on September 11-12 2008.

This interesting workshop is organized by the IEEE EDS Compact Modeling Technical Committee, in collaboration with the London Center for Nanotechnology, University College of London, UK, the Electrical Engineering Division, Engineering Department, Cambridge University, UK, and the IEEE UK-RI (AP/ED/LEO/MTT) joint Chapter.

Compact modeling of TFTs has become nowadays a very hot topic, due to the extension of the applications of TFTs. This workshop will provide a forum for discussions and current developments on compact TFT modeling.

Topics include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for abstract submission is July 15.

I will give an invited presentation in this workshop. And there will be other interesting invited presentations.

This is the first workshop that is devoted to compact TFT modeling. I recommend the TFT modeling and TFT circuit design communities to attebnd this workshop.

Besides, in conjunction with the workshop on “Compact TFT Modeling for Circuit Simulation,” IEEE Electron Devices Society (EDS) Compact Modeling Technical Committee (CMTC) in collaboration with IEEE UK-RI AP/ED/LEO/MTT Chapter has organized EDS mini-colloquia (MQ) on September 12, 2008 at Moller Centre, Cambridge, UK.

SINANO-NANOSIL Workshop

The SINANO-NANOSIL Workshop will take place in Edinburgh on September 19th, 2008, during the ESSDERC-ESSCIRC Conference.

This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices. The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.

The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:

9:00 New channel materials for ultimate CMOS
Siegfried Mantl (Institut für Bio- und Nanosysteme, Forschungszentrum Juelich)

9:30 Innovative device architectures for Nanoscale CMOS
Nadine Collaert (IMEC)

10:00 Coffee break

10:30 Comparative analysis of Stress-induced performance enhancement in NMOS and PMOS transistors
David Esseni (Udine University)

11:00 Characterization methods for Nanodevices
Sorin Cristoloveanu (IMEP)

11:30 Emerging Nanotechnology for integration of Nanostructures in Nanoelectronic devices
Thierry Baron (LTM)

12:00 Lunch

13:30 Small Slope Switches
Adrian Ionescu (EPFL)

14:00 3D Multichannels and stacked Nanowires Technologies
Thomas Ernst (LETI)

14:30 Carbon Nanotube - Silicon heterojunctions for Nanoelectronics and Nanosensors
Jimmy Xu (Brown University)

15:00 Atomic functionalities in Silicon devices: go beyond the FET by using single dopants and artificial silicon atoms
Marc Sanquer (INAC)

15:30 End of the Workshop