IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation

The first IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation will be held in the Moller Center, in Cambridge, UK, on September 11-12 2008.

This interesting workshop is organized by the IEEE EDS Compact Modeling Technical Committee, in collaboration with the London Center for Nanotechnology, University College of London, UK, the Electrical Engineering Division, Engineering Department, Cambridge University, UK, and the IEEE UK-RI (AP/ED/LEO/MTT) joint Chapter.

Compact modeling of TFTs has become nowadays a very hot topic, due to the extension of the applications of TFTs. This workshop will provide a forum for discussions and current developments on compact TFT modeling.

Topics include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for abstract submission is July 15.

I will give an invited presentation in this workshop. And there will be other interesting invited presentations.

This is the first workshop that is devoted to compact TFT modeling. I recommend the TFT modeling and TFT circuit design communities to attebnd this workshop.

Besides, in conjunction with the workshop on “Compact TFT Modeling for Circuit Simulation,” IEEE Electron Devices Society (EDS) Compact Modeling Technical Committee (CMTC) in collaboration with IEEE UK-RI AP/ED/LEO/MTT Chapter has organized EDS mini-colloquia (MQ) on September 12, 2008 at Moller Centre, Cambridge, UK.

SINANO-NANOSIL Workshop

The SINANO-NANOSIL Workshop will take place in Edinburgh on September 19th, 2008, during the ESSDERC-ESSCIRC Conference.

This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices. The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.

The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:

9:00 New channel materials for ultimate CMOS
Siegfried Mantl (Institut für Bio- und Nanosysteme, Forschungszentrum Juelich)

9:30 Innovative device architectures for Nanoscale CMOS
Nadine Collaert (IMEC)

10:00 Coffee break

10:30 Comparative analysis of Stress-induced performance enhancement in NMOS and PMOS transistors
David Esseni (Udine University)

11:00 Characterization methods for Nanodevices
Sorin Cristoloveanu (IMEP)

11:30 Emerging Nanotechnology for integration of Nanostructures in Nanoelectronic devices
Thierry Baron (LTM)

12:00 Lunch

13:30 Small Slope Switches
Adrian Ionescu (EPFL)

14:00 3D Multichannels and stacked Nanowires Technologies
Thomas Ernst (LETI)

14:30 Carbon Nanotube - Silicon heterojunctions for Nanoelectronics and Nanosensors
Jimmy Xu (Brown University)

15:00 Atomic functionalities in Silicon devices: go beyond the FET by using single dopants and artificial silicon atoms
Marc Sanquer (INAC)

15:30 End of the Workshop

AM-FPD'08

The 15th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD-08, former AM-LCD) will be held from July 2 to 4 2008 at the National Museum of Emerging Science and Innovation (Miraikan), Tokyo, Japan.

AM-FPD has extended the goals of former AM-LCD workshop in order to address, apart from AM-LCD technology, AM-OLED displays and other AM-FPD technologies. The topics of AM-FPD also include TFT devices, circuits and systems, LC technologies, related materials and crystallization.

Besides, a symposium "Emerging Technologies for Future Displays" is scheduled. This symposium will consist of four sessions: "Basic properties for fututre TFTs", "Advanced TFT technologies for future applications", "Technologies for LCD" and "Future technologies for Organic Devices".

The authors of the best papers will be invited to submit extended versions of their papers for publication in the Japanese Journal of Applied Physics, in a special issue called "Active-Matrix Flatpanel Displays and Devices-TFT Technologies and FPD Materials".

AM-FPD is one of the top conferences in the field of TFTs. Papers are very interesting, and include several invited presentations.

A number of papers address TFT compact modeling. H. Ikeda (Sony, Japan) presents one paper entitled "Surface Potential-BAsed Polycrystalline- Silicon TFT Model for Circuit Simulation". M. Kimura (Ryukoku University, Japan) presents "Physical Model of Current-Voltage Characteristic for TFT".

Other papers address issues such as LCD & FPDs, TFT crystallization technologies, TFT process technologies, characterization and reliability of TFTs, OLEDs, Oxide Semiconductor TFTs, and new applications of TFTs

BMAS'08

The 2008 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2008) will be held in San Jose, CA, on September 25-26, in conjunction with the 2008 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.

BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. One of the main areas of topics is "Semiconductor Device Compact Modeling", which includes: " Compact device modeling lanuages and compilers", "Standard and new compact device models implemented in Verilog-A and VHDL-AMS", and "Compact device models for emerging technologies and topical issues (nano-devices, distributed thermal effect, leakaging issues, manufacturability, radiation effects, etc)".

The deadline for paper submission is June 30 2008.

For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.

Edinburgh ESSDERC/ESSCIRC Workshop: 1st announcement for MOS-AK

I post the announcement I've got from Wladek Grabinski concerning the MOS-AK Workshop:

MOS-AK Workshop on compact modeling, organized for sixth subsequent time as an
integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network
and discussion forum among experts in the field, create an open platform for
information exchange related to compact/Spice modeling, bring people in the
compact modeling field together, as well as obtain feedback from technology
developers, circuit designers, and CAD tool vendors.

The topics of the Workshop cover all important aspects of compact model development,
implementation, deployment and standardization within the main theme - compact models
for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to
classify the most important directions for the future development of the compact
models and to clearly identify areas that need further research.

This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe)
who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC)
and those starting in that area as well as device characterization, modeling and
parameter extraction engineers. The content will be beneficial for anyone who needs
to learn what is really behind IC simulation in modern device models.

The technical program of MOS-AK Workshop consists of one day of tutorials given by
noted academic and industry experts, also a posters session is foreseen which will
be dedicated but not limited to the VHDL-AMS/Verilog-A model standardization:

http://www.mos-ak.org/edinburgh

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

Tentative list of the speakers already includes following names:
 * Narain Arora, Silterra
 * David M. Binkley, UNC Charlotte
 * Matthias Bucher, TUC
 * Christian Enz, CSEM
 * Benjamin Iniguez, URV
 * Tom J. Kazmierski, University of Southampton
 * Ehrenfried Seebacher, austriamicrosystems
 * Sadayuki Yoshitomi, TOSHIBA

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

--- Important dates:
--------------------
* 2nd announcement       - July 19
* Final workshop program -  Aug.19
* MOS-AK Workshop        - Sept.19 at the Edinburgh International Conference
Centre (EICC)

Further information including recommended hotels and driving directions will be
posted at our web site, soon; please visit regularly: http://www.mos-ak.org

Let me remark that this is also a nice opportunity to visit Edinburgh (see these
links 1 and 2), and make some whisky tasting (see the links 1 and 2)!

Graduate Student Meeting on Electronic Engineering

The Graduated Student Meeting on Electronic Engineering (formerly Nanoelectronics and Photonics Systems Workshop), has been an annual event, created and organized by the Universitat Rovira i Virgili (URV), in Tarragona (Catalonia, Spain) since 2003. It consists of two days of plenary talks given by invited prestigious researchers (from different countries) about selected topics related to electronic engineering and two poster sessions were PhD students in this field will present their work.

This Graduated Student Meeting has become a very useful forum for PhD students and researchers in the field of Electronic Engineering. The present edition will take place in June 19th and 20th.

This year, the Graduated Student Meeting is being sponsored by the NANOSIL European Network of Excellence. One of the invited speakers, Prof. Sorin Cristoloveanu (IMEP-INP Grenoble, France), is one of the leading authorities in the field of SOI technology and characterization. His talk is entitled "Selected Characterization Techniques for SOI Materials and Devices"

Another invited speaker, Prof. Antonio Cerdeira (CINVESTAV, Mexico City) will conduct a lecture on "Compact Model for Symmetric Double-Gate MOSFETS"
Prof Cerdeira has a long experience and outstanding publicactions in compact model and every year spends several months as an invited researcher in the Universitat Rovira i Virgili.

Both Prof. Cristoloveanu and Prof. Cerdeira have been invited as Distinguished Lecturers of the Electron Devices Society of the IEEE.

Other talks will address photonic crystals (Dr D Gerace), dynamical systems (Dr B Robert) and nanorods (Dr C Blackman).

Awards for the best posters in two categories: one category for Master students and another category for Doctoral Students.

2-pages abstracts corresponding to poster presentations and plenary talks will be published in the Proceedings. The deadline for abstracts reception is June 11th.

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

In June the weather is warm enough to go to the beaches in or around Tarragona, but comfortable enough to walk and do sightseeing in the city. Thanks to its Mediterranean climate, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I encourage Ph D students to send posters and attend this interesting Meeting!

Adieu Electronics: The End is Near (Perhaps Nearer than You Think)

I've been reading a very interesting post in Electronics Design, Strategy, News. The author, Steve Leibson, says that it seems we're running out of some of the necessary elements in semiconductor fabrication... Have a look at the post, and don't miss the comments....

In any case, it seems that this is a very good moment to be developing models for new devices! :-)