Sunday, 8 June 2008

Edinburgh ESSDERC/ESSCIRC Workshop: 1st announcement for MOS-AK

I post the announcement I've got from Wladek Grabinski concerning the MOS-AK Workshop:

MOS-AK Workshop on compact modeling, organized for sixth subsequent time as an
integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network
and discussion forum among experts in the field, create an open platform for
information exchange related to compact/Spice modeling, bring people in the
compact modeling field together, as well as obtain feedback from technology
developers, circuit designers, and CAD tool vendors.

The topics of the Workshop cover all important aspects of compact model development,
implementation, deployment and standardization within the main theme - compact models
for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to
classify the most important directions for the future development of the compact
models and to clearly identify areas that need further research.

This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe)
who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC)
and those starting in that area as well as device characterization, modeling and
parameter extraction engineers. The content will be beneficial for anyone who needs
to learn what is really behind IC simulation in modern device models.

The technical program of MOS-AK Workshop consists of one day of tutorials given by
noted academic and industry experts, also a posters session is foreseen which will
be dedicated but not limited to the VHDL-AMS/Verilog-A model standardization:

http://www.mos-ak.org/edinburgh

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

Tentative list of the speakers already includes following names:
* Narain Arora, Silterra
* David M. Binkley, UNC Charlotte
* Matthias Bucher, TUC
* Christian Enz, CSEM
* Benjamin Iniguez, URV
* Tom J. Kazmierski, University of Southampton
* Ehrenfried Seebacher, austriamicrosystems
* Sadayuki Yoshitomi, TOSHIBA

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

--- Important dates:
--------------------
* 2nd announcement - July 19
* Final workshop program - Aug.19
* MOS-AK Workshop - Sept.19 at the Edinburgh International Conference
Centre (EICC)

Further information including recommended hotels and driving directions will be
posted at our web site, soon; please visit regularly: http://www.mos-ak.org

Let me remark that this is also a nice opportunity to visit Edinburgh (see these
links 1 and 2), and make some whisky tasting (see the links 1 and 2)!

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