This video explains and demonstrates a method to develop accurate SPICE models from verified S-parameter measurements. By using an easy to follow, step by step procedure, this video walks you through the entire modeling flow for an on-wafer capacitor, using the Keysight Measurement and Modeling Software IC-CAP.
The IC-CAP project can be downloaded, together with a detailed How-to-Use description, and an in-depth tutorial about passive components modeling, applying the demonstrated method.
[VIDEO]
Dec 16, 2015
Nov 18, 2015
[mos-ak] [Final Program] 8th International MOS-AK Workshop Washington DC December 9, 2015
8th International MOS-AK Workshop
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Washington DC December 9, 2015
The Final MOS-AK Workshop Program
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Washington DC in the IEDM / CMC meetings timeframe on December 9, 2015. The MOS-AK workshop is organized with aims to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Venue:
Embassy of Switzerland
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
2900 Cathedral Ave, NW,
Washington, DC 20008
USA
Free Online Workshop Registration:
http://www.mos-ak.org/washington_dc_2015/registration.php
(any related inquiries can be sent to register@mos-ak.org)
(any related inquiries can be sent to register@mos-ak.org)
Workshop Agenda:
- MOS-AK Workshop - Dec, 9, 2015
- Online Technical Program http://www.mos-ak.org/
washington_dc_2015/ - 08:30 - 09:00 - On-site Registration
- 09:00 - 12:30 - Morning MOS-AK Session
- TCAD and Advanced CMOS Technologies
- Compact Modeling and Reliability Co-simulation
- 12:30 - 13:30 - Lunch
- 13:30 - 17:00 - Afternoon MOS-AK Session
- CMC Compact Model Standardization
- FOSS Tools for Compact Model Verilog-A Standardization
- 17:00 End of the workshop
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)
Extended MOS-AK Committee
WG/18/11/15
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Nov 11, 2015
[ESSCIRC 2015] Low-power analog RF circuit design based on the inversion coefficient
[ref] Enz, Christian; Chalkiadaki, Maria-Anna; Mangla, Anurag, "Low-power analog/RF circuit design based on the inversion coefficient," in ESSCIRC 2015 - 41st , vol., no., pp.202-208, 14-18 Sept. 2015
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Abstract: This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.
Keywords: Analytical models, Integrated circuits, Noise, Radio frequency, Silicon, Transconductance, Transistors, BSIM6
URL / doi: 10.1109/ESSCIRC.2015.7313863
Labels:
Analytical models,
BISM6,
ekv,
gm/ID,
IC,
Integrated circuits,
mosfet,
noise,
Radio frequency,
rf,
Silicon,
Transconductance,
Transistors
Location:
Graz, Austria
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