Mar 30, 2020

conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

#paper Y. Nakamura, N. Kuroda, T. Yanagi, H. Sakairi and K. Nakahara, "High-Voltage and High-Current Id–Vds Measurement Method for Power Transistors Improved by Reducing Self-Heating," in IEEE EDS (Open Access), vol. 41, no. 4, pp. 581-584, April 2020. https://t.co/85eA0jPQKb https://t.co/PT6CUQRELM


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March 30, 2020 at 09:52AM
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Mar 29, 2020

#paper: T. Mikolajick, U. Schroeder and S. Slesazeck, "The Past, the Present, and the Future of Ferroelectric Memories," in IEEE TED, vol. 67, no. 4, pp. 1434-1443, April 2020. https://t.co/OmPJ0xf6wU https://t.co/jWifCPdJ1D


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March 29, 2020 at 06:08PM
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#paper: Scientists from the POWERlab at #EPFL, have built a nanodevice capable of producing high-power Terahertz (#THz) waves https://t.co/Cl6jBInynx https://t.co/4PIJmN6Jpm


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March 29, 2020 at 05:38PM
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#paper: EKV Transistor Model For Ultra Low-Voltage Bulk-Driven Circuits


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March 29, 2020 at 04:33PM
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Mar 27, 2020

The Art of Reverse Engineering appeared first on #OpenSource For You https://t.co/B1sKAzlzAh https://t.co/OZ4ErMqS0Y


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March 27, 2020 at 04:44PM
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#paper: Q. Huo et al., "A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond," in IEEE J-EDS, vol. 8, pp. 295-301, 2020 DOI: 10.1109/JEDS.2020.2980441 https://t.co/QrqdHdvHmT https://t.co/vTr39EBQ6r


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March 27, 2020 at 10:23AM
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