Changing Direction In Chip Design https://t.co/XV84VQnO71 #semi #feedly #papers

Changing Direction In Chip Design https://t.co/XV84VQnO71 #semi #feedly #papers

— Wladek Grabinski (@wladek60) January 26, 2017

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year’s Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and where are the holes that need to be filled.

from Twitter https://twitter.com/wladek60

January 26, 2017 at 08:12PM
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[EUROSOI ULIS] Deadline for abstract submission extended to January 29, 2017

Submit your abstract for  Conference to be held in Athens in April 2017 as soon as possible. We would like to inform you that, due to several requests, the deadline for abstract submission has been extended to January 29, 2017, Please note that there will be both Oral and Poster Sessions 

Call for Papers

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The accepted abstracts will be published in a Proceedings book with an ISBN. A 4-page follow-up paper delivered before will be published in IEEE Xplore Digital Library. The authors of the best papers will be invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO Institute. Both an Oral and a A Poster Session will be organized.

INVITED SPEAKERS

Prof. Maryline Bawedin, IMEP - INP Grenoble MINATEC, "The mystery of the Z2-FET 1T-DRAM memory"

Dr. Frank Schwierz, University of Ilmenau, "The Prospects of 2D Materials for Ultimately-Scaled CMOS"

Dr. Cosmin Roman, ETH Zurich, "Micro and Nano transducers for autonomous sensing applications"

Dr. Carlo Cagli,  CEA-LETI,  "Memories"

Dr. Anda Mocuta, IMEC, "Nanoscale FET"

The EUROSOI ULIS Conference Chairperson: 

Prof. Androula G. Nassiopoulou

NCSR Demokritos 

Institute of Nanoscience and Nanotechnology, 

Athens, Greece 

#TCAD Simulation of #Organic #Optoelectronic #Devices https://t.co/k7iZDQjppR #papers

#TCAD Simulation of #Organic #Optoelectronic #Devices https://t.co/k7iZDQjppR #papers

— Wladek Grabinski (@wladek60) January 23, 2017

from Twitter https://twitter.com/wladek60

January 23, 2017 at 09:47AM
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2016 Phil Kaufman Award Recipient: Dr. Andrzej Strojwas

Kaufman Award Dinner: Why you should Attend

IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.

This year’s Kaufman Award Dinner promises to be an inspiring evening, one that will help you remember why you went to work here in the first place [read more...]

If you want to attend, you can register here.

[mos-ak] [2nd Announcement and Call for Papers] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  

   at DATE Conference in Lausanne, March 31, 2017
     2nd Announcement and Call for Papers   

 
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Dec. 2016
  
• Call for Papers - Jan. 2017
  
• Final Workshop Program - Feb. 2017
  
• MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
  
• Advances in semiconductor technologies and processing
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, TFT, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
  
• Foundry/Fabless Interface Strategies
  

Online MOS-AK Abstract Submission:
Prospective authors should submit abstract online 

http://www.mos-ak.org/lausanne_2017/abstracts.php

(any related inquiries can be sent to abstrscts@mos-ak.org)

Online Workshop Registration (to be open Feb.2017):

http://www.mos-ak.org/lausanne_2017 
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG17012017

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[mos-ak] [press note] 9th International MOS-AK Workshop at UC Berkeley, Dec.7, 2016

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

9th International MOS-AK Workshop

(co-located with the CMC Meeting and IEDM Conference)

December 7, 2016 Berkeley

The MOS-AK Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual Q4 event on December 7, 2016 UC Berkeley as its 9th consecutive International MOS-AK Workshop. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was hosted by Prof. Jaijeet Roychowdhury of EECS at the University of California at Berkeley and co-sponsored by Keysight Technologies and NEEDS of nanoHUB.org.

The workshop provided presentations from the leading developers of compact device models. The audience spanned the full range of the semiconductor industry, including representatives from foundries, model characterization services firms, academic researchers investigating emerging device technologies, and design companies. The amount and breadth of technical information discussed was vast -- here are but a few highlights by ChipGuy:
<https://www.semiwiki.com/forum/content/6542-its-all-about-models.html>

These were but a few of the technical highlights and achievements discussed at the workshop which are available online:
<http://www.mos-ak.org/berkeley_2016>

The MOS-AK Modeling Working Group has various deliverables and initiatives, including: a book entitled "Open Source CAD Tools for Compact Modeling" <www.mos-ak.org/books>; an open Verilog-A directory with compact models <http://www.mos-ak.org/open_dir/>; and supporting FOSS TCAD/CAD software.

The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017 year, including:

• Spring MOS-AK Workshop in Lausanne at DATE Conference (March 31 2017) 
  <http://www.mos-ak.org/lausanne_2017>
  
• 2nd Sino MOS-AK Workshop in Hangzhou (June 2017) 
  <http://www.mos-ak.org/hangzhou_2017>
  
• 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017) 
  <http://www.mos-ak.org/leuven_2017>

If you are involved in developing or supporting device models for circuit designers, we would encourage you to become an active participant in the MOS-AK community.

About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.

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[paper] Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s 

Using Universal Rad-SPICE MOSFET Model

Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov

J Electron Test (2017)

doi:10.1007/s10836-016-5635-8

Abstract: The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.

The electrical schematics of SOS CMOS opamp and 4-bit counter are presented; two variants of either macromodel were used for body-tied partially-depleted transistors: a) core EKV-SOI/ BSIMSOI model; b) EKV-RAD/ BSIMSOI-RAD macromodel. [read more...]