New SPICE Model for Silicon Carbide Power MOSFET

Cree Releases SPICE Model for Silicon Carbide Power MOSFET

Behavior-based model enables power electronic design engineers to quantify benefits of silicon carbide MOSFETs in board-level circuit simulation

See the original press release, or read it here:

DURHAM, N.C., February 6, 2012 — Cree, Inc. (Nasdaq: CREE), a market leader in silicon carbide (SiC) power devices, has expanded its design-in support for the industry’s first commercially-available SiC MOSFET power devices with a fully-qualified SPICE model. Using the new SPICE model, circuit designers can easily evaluate the benefits Cree’s SiC Z-FET™ MOSFETs provide for achieving a higher level of efficiency than is possible with conventional silicon power switching devices for comparably-rated devices.

SiC MOSFETs have significantly different characteristics than silicon devices and therefore require a SiC-specific model for accurate circuit simulations. Cree’s behavior-based, temperature-dependent SPICE model is compatible with the LT spice simulation program and enables power electronics design engineers to reliably simulate the advanced switching performance of Cree CMF10120D and CMF20120D Z-FETs in board-level circuit designs.

Cree SiC MOSFETs are capable of delivering switching frequencies that are up to 10 times higher than IGBT-based solutions. Their higher switching frequencies can enable smaller magnetic and capacitive elements, thereby shrinking the overall size, weight and cost of power electronics systems.

This SiC MOSFET SPICE model adds to Cree’s comprehensive suite of design-in support tools, technical documentation, and reliability information to provide power electronics engineers with the design resources necessary to implement SiC power devices into the next generation of power systems.

The Cree SiC MOSFET SPICE model is available for download at www.cree.com/power/mosfet.asp. In addition, customers can download published specifications and detailed design guidelines and request samples. For more information about Cree’s SiC power devices, please visit www.cree.com/power.

About Cree
Cree is a market-leading innovator of semiconductor products for power and radio-frequency (RF) applications, lighting-class LEDs, and LED lighting solutions.

Cree's product families include LED fixtures and bulbs, blue and green LED chips, high-brightness LEDs, lighting-class power LEDs, power-switching devices and RF devices. Cree products are driving improvements in applications such as general illumination, electronic signs and signals, power supplies and solar inverters.

For additional product and company information, please refer to www.cree.com

This press release contains forward-looking statements involving risks and uncertainties, both known and unknown, that may cause actual results to differ materially from those indicated. Actual results may differ materially due to a number of factors, including customer acceptance of our products; the rapid development of new technology and competing products that may impair demand or render Cree’s products obsolete; and other factors discussed in Cree’s filings with the Securities and Exchange Commission, including its report on Form 10-K for the year ended June 26, 2011, and subsequent filings.

Cree is a trademark registered in the U.S. Patent and Trademark Office by and Z-FET is a trademark of Cree, Inc.

Media Contact:
Michelle Murray
Cree, Inc.
Corporate Communications
(919) 313-5505
michelle_murray@cree.com

SISPAD 2012, Denver, CO, USA, Call for Papers

Call for Papers The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of the leading-edge research and development results in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. Date and Location Conference date: September 5-7, 2012 Abstract submission deadline: April 1, 2012 Conference location: Sheraton Denver Downtown Hotel, Denver, Colorado, USA Webpage: http://www.ece.umd.edu/sispad2012 Topics Original papers are solicited in the following subject areas: Electronic Transport in Semiconductor Materials and Devices Device Modeling and Simulation Sensors, Biosensors and Electromechanical Systems Simulation Process and Equipment Modeling and Simulation Compact Models Physical-Level Circuit Simulation New Algorithms for Process and Device Modeling Simulation of Nano and Quantum Devices User Interfaces and Visualization Simulation of Power Devices Photovoltaics and Other Green Technologies The abstract should describe the nature of the presentation, together with references. The text must be single-spaced with 11pt or 12pt font. The abstract is limited to two pages including figures, tables and references. Abstracts should be submitted in PDF format. For more information, please visit: http://www.ece.umd.edu/sispad2012/

 

Execs gather at SEMI ISS

From Semiconductor Manufacturing and Design:

At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.

Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.

The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.

TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.

KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.

SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."

[mos-ak] C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18, 2012

C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18,
2012

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
JIIT, Noida (U.P.) India, March 16-18, 2012 with the tutorial on CMOS
technology and SPICE Models by Dr. N.D. Arora, Silterra, Malaysia.

List of the international modeling experts contributing to the MOS-AK/
GSA Workshop includes following names (in alphabetic order)
* Nanrian D. Arora, Silterra, Malaysia
* Navakanta Bhat, IISC Bangalore, India
* A.B. Bhattacharyya, JIIT Noida, India
* Mike Brinson, London Metropolitan University, UK
* Amitava Dasgupta, IIT Chennai, India
* Christian Enz, EPFL, Switzerland
* Tamilmani Ethirajan, IBM, India
* Thomas Gneiting, ADMOS, Germany
* Wladek Grabinski, MOS-AK/GSA
* Andre Juge, STM, France
* M. Jagdesh Kumar, IIT Delhi, India
* Shantanu Mahapatra, IISc, India
* Mitiko Miura-Mattausch, Hiroshima University, Japan
* Ramgopal Rao, IIT Mumbai
* Samar Saha, IEEE
* Manoj Saxena, University of Delhi, India
* Ehrenfried Seebacher, AMS, Austria
* Vaidyanathan Subramanian, IBM, India
* Xing Zhou, NTU, Singapore

The terms of participation:
* To register please visit the INAE website <http://inae.org/
seminar.htm> and complete the registration form
* Poster abstract submission with the deadline on Jan. 31, 2012.
Posters' abstract of maximum 300 words and paper of maximum 5 pages in
A4 size double spaced two columns should be submitted to Prof. AB
Bhattacharyya at <inaehq@gmail.com>

Intending participants and authors should also note the following
deadlines:
* Announcement and Call for Papers - Q4 2012
* Poster abstract submission deadline - Jan.31, 2012
* Final Workshop Program - Feb. 2012
* MOS-AK/GSA Workshop - March 16-18, 2012

Further details and updates: <http://www.mos-ak.org/india>
Email contact: <india@mos-ak.org>

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[mos-ak] MOS-AK/GSA Washington DC on-line publications

MOS-AK/GSA Washington DC workshop on-line publications are available,
visit:
http://mos-ak.org/washington_dc/

I would like to thank all MOS-AK/GSA speakers for sharing their
compact modeling competence, R&D experience and delivering valuable
MOS-AK/GSA presentations. I am sure, that our modeling event in
Washington DC was a beneficial on to all the attendees as well as to
all MOS-AK/GSA Group.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
http://mos-ak.org/committee.html
––––––––––––––––––––––––––––––––––----------------
MOS-AK/GSA India March 16-17, 2012
<http://mos-ak.org/india/>
MOS-AK/GSA Dresden April 26-27, 2012
<http://mos-ak.org/dresden/>
MIXDES Special Modeling Sesion Warsaw May 24-26, 2012
<https://www.mixdes.org/Special_sessions.htm>
MOS-AK/GSA Bordeaux Sept.21, 2012
<http://goo.gl/bUrsp>
MOS-AK/GSA San Francisco Q4 2012
––––––––––––––––––––––––––––––––––----------------

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EPFL Post-doctoral/ experienced engineer position

Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at developing new technologies based on low power wireless communications, for communication between one intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain (RF IC group leader) is the scientific coordinator of this project. 

We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated circuits with strong practical experience in the following topics:

• Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks) 
• Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
• Design of CMOS power management circuits 
• Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications 
• Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc) 

The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.

• Starting date: as soon as possible. 
• Contract duration: 18 months 

Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain

C4P: 2012 IEEE Silicon Nanoelectronics Workshop

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society

Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices. Download the Call for Papers (PDF format) Further Information The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome. Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.

Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
Scope:
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]