Some new papers on the Volume 52, Issue 6, Pages 839-996 (June 2008) of Solid-State Electronics.
A universal electron mobility model of strained Si MOSFETs based on variational wave functions
Renrong Liang, Debin Li and Jun Xu
Substrate current characterization and optimization of high voltage LDMOS transistors
Jun Wang, Rui Li, Yemin Dong, Xin Zou, Li Shao and W.T. Shiau
Small-signal performance and modeling of sub-50 nm nMOSFETs with fT above 460-GHz
V. Dimitrov, J.B. Heng, K. Timp, O. Dimauro, R. Chan, M. Hafez, J. Feng, T. Sorsch, W. Mansfield, J. Miner, A. Kornblit, F. Klemens, J. Bower, R. Cirelli, E.J. Ferry, A. Taylor, M. Feng and G. Timp
Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics
Sébastien Frégonèse, Yan Zhuang and Joachim N. Burghartz
A physical model of floating body effects in polysilicon thin film transistors
W.J. Wu, R.H. Yao, T. Chen, R.S. Chen, W.L. Deng and X.R. Zheng
Enjoy your reading!
May 6, 2008
Synopsys Launches HSPICE Integrator Program With 25 Founding Members
It seems that Synopsys is trying to get back the leading position in the simulators market. Have a look at the post in their news section (disregard the self-publicity they do... it's natural in a company...). I copy here the post, because the final destination of a compact model is to be implemented... and one has to know which are the leading tools...
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today launched its HSPICE® Integrator Program to further promote integration between Synopsys' HSPICE simulation solution and other electronic design automation (EDA) products. The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
Founding members of the HSPICE Integrator Program include: Accelicon Technologies Inc., Agilent EEsof EDA, Altos Design Automation, Inc., Apache Design Solutions, Applied Simulation Technology, ATEEDA, AWR, Computer Simulation Technology (CST), Helic S.A., Interra Systems Inc., Jedat Inc., Mephisto Design Automation (MDA), MunEDA GmbH, Nangate Inc., Novas Software, OEA International, Inc., Orora Design Technologies, Inc., Physware, Inc., ProPlus Design Solutions, Inc., Signal Integrity Software, Inc. (SiSoft), Sigrity, Inc., Silicon Canvas, Solido Design Automation Inc., Veritools Inc., and Z Circuit Automation. For more information, visit the HSPICE Integrator Program, http://www.synopsys.com/hspice_integrator/
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today launched its HSPICE® Integrator Program to further promote integration between Synopsys' HSPICE simulation solution and other electronic design automation (EDA) products. The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
Founding members of the HSPICE Integrator Program include: Accelicon Technologies Inc., Agilent EEsof EDA, Altos Design Automation, Inc., Apache Design Solutions, Applied Simulation Technology, ATEEDA, AWR, Computer Simulation Technology (CST), Helic S.A., Interra Systems Inc., Jedat Inc., Mephisto Design Automation (MDA), MunEDA GmbH, Nangate Inc., Novas Software, OEA International, Inc., Orora Design Technologies, Inc., Physware, Inc., ProPlus Design Solutions, Inc., Signal Integrity Software, Inc. (SiSoft), Sigrity, Inc., Silicon Canvas, Solido Design Automation Inc., Veritools Inc., and Z Circuit Automation. For more information, visit the HSPICE Integrator Program, http://www.synopsys.com/hspice_integrator/
May 5, 2008
Memristor
A friend of us (Francisco J. Garcia) has pointed out a recent paper in Nature Letters (Vol 453| 1 May 2008| doi:10.1038/nature06932). I post here the abstract, because it is very interesting, though not very related to compact modeling:
Authors: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams
ABSTRACT: Anyone who ever took an electronics laboratory class will be familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor. However, in 1971 Leon Chua reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor). Although he showed that such an element has many interesting and valuable circuit properties, until now no one has presented either a useful physical model or an example of a memristor.
Here we show, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. These results serve as the foundation for understanding a wide range of hysteretic current–voltage behaviour observed in many nanoscale electronic devices2–19 that involve the motion of charged atomic or molecular species, in particular certain titanium dioxide cross-point switches20–22.
There is a remarks to be done, following Francisco, since you can find a patent of a very similar device:
Genrikh et al
US Patent Application Publication No. US 2007/0200158 A1, Aug. 30, 2007
ELECTRODE STRUCTURE HAVING AT LEAST TWO OXIDE LAYERS AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME
Assignee: Samsung Electronics, Co., Ltd.
Filed: Jan. 19, 2007
Authors: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams
ABSTRACT: Anyone who ever took an electronics laboratory class will be familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor. However, in 1971 Leon Chua reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor). Although he showed that such an element has many interesting and valuable circuit properties, until now no one has presented either a useful physical model or an example of a memristor.
Here we show, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. These results serve as the foundation for understanding a wide range of hysteretic current–voltage behaviour observed in many nanoscale electronic devices2–19 that involve the motion of charged atomic or molecular species, in particular certain titanium dioxide cross-point switches20–22.
There is a remarks to be done, following Francisco, since you can find a patent of a very similar device:
Genrikh et al
US Patent Application Publication No. US 2007/0200158 A1, Aug. 30, 2007
ELECTRODE STRUCTURE HAVING AT LEAST TWO OXIDE LAYERS AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME
Assignee: Samsung Electronics, Co., Ltd.
Filed: Jan. 19, 2007
Apr 30, 2008
Process for the Selection of the Next Generation SOI MOSFET Compact Models
The Compact Modeling Council (CMC) has started the Process for the Selection of the Next Generation SOI MOSFET Compact Models.
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
Training Course on SOI for analog,digital and RF SOCs and microsystems applications
This training course on SOI for analog,digital and RF SOCs and microsystems applications will take place at IMEC (Heverlee, Belgium) on May 15-16 2008.
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
Course: "New Trends in Nanoelectronics" in Lausanne
The course "New Trends in Nanoelectronics" will be organized by Prof. Adrian M. Ionescu, from EPFL (Lausanne, Switzerland). This two-day course will take place in Lausanne on May 22-23 2008.
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
Apr 29, 2008
Open Ph D Student position in nanoelectronic device modeling
We offer one fellowship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in
The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel nanoscale semiconductor devices. It will be related to two European projects in which the hosting group participates.
To get more information about our areas of research in the DEEEA, you can visit the website:
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/scholarships.htm
And
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos
Required documents for applicants
Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible)
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours of each subject). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we suggest to send the documents by postal mail.
Applications should be sent to:
Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610
Deadline:
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information
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