[https://t.co/Jk28F7d8do] Verification In #OpenSource Era https://t.co/3Skg6dmbqz #SEMI pic.twitter.com/I86bPeSKMA
— Wladek Grabinski (@wladek60) March 25, 2021
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March 25, 2021 at 02:43PM
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Mar 25, 2021
[https://t.co/Jk28F7d8do] Verification In #OpenSource Era https://t.co/3Skg6dmbqz #SEMI https://t.co/I86bPeSKMA
from Twitter https://twitter.com/wladek60
March 25, 2021 at 02:43PM
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Mar 23, 2021
[mos-ak] [2nd Announcement and C4P] 3rd MOS-AK LAEDC Workshop (virtual/online) April 18, 2021
2nd Announcement and C4P
Together with local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to 3rd consecutive MOS-AK Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on April 18, 2021 preceding the LAEDC Conference.
Planned virtual 3rd MOS-AK LAEDC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.
Venue: Virtual/Online at LAEDC Conference
Online Workshop Registration to be in April 2021,
any related enquiries can be sent to registration@mos-ak.org
Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based memory cells
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
- Technology R&D, DFY, DFT and reliability/aging IC designs
- Foundry/Fabless Interface Strategies
Online Abstract Submission to be open,
any related enquiries can be sent to abstracts@mos-ak.org
Important Dates:
- Call for Papers - Dec. 2020
- 2nd Announcement - March 2020
- Final Workshop Program - April 2020
- MOS-AK Workshop April 18, 2021
W.Grabinski for Extended MOS-AK Committee
WG23032021
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[EETimes] (Re)Shoring Up #semi Manufacturing - https://t.co/fNy0FgOiEG https://t.co/mVhn0SPjOS
[EETimes] (Re)Shoring Up #semi Manufacturing - https://t.co/fNy0FgOiEG pic.twitter.com/mVhn0SPjOS
— Wladek Grabinski (@wladek60) March 23, 2021
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March 23, 2021 at 03:22PM
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Virtual Si Museum /2111/ E.Eng Tools
This is how I was introduced to the engineering. My very fist log rule and my HP-21 scientific calculator (successor of the famous HP-35)
REF:
[1] Slide rule: https://en.wikipedia.org/wiki/Slide_rule
[2] HP-21 scientific calculator: https://en.wikipedia.org/wiki/HP-21
[Extended C4P] ESSDERC Track3 "Compact Modeling and Process/Device Simulation"
51st European Solid-State Device Research Conference ESSDERC
47th European Solid-State Circuits Research Conference ESSCIRC
will be held together in hybrid format in Grenoble in September this year
• Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection.• Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, High voltage and Power, emerging technologies and novel devices), parameter extraction, reliability and variability, performance evaluation and open source benchmarking/implementation methodologies.• Modeling of interactions between process, device and circuit design, Design Technology Co-Optimization, Foundry/Fabless Interface Strategies.• Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration; Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, …); Mechanical or electro-thermal modeling and simulation; DfM.• Reliability of materials and devices.• Design Technology-Co-Optimization.
The deadline for the submission of abstracts is
Thierry Poiroux, CEA-LETI (F) - Track3 Chair
Compact Modeling and Process/Device Simulation
https://www.esscirc-essderc2021.org/
Mar 20, 2021
[C4P] 32nd MIEL 2021
32nd IEEE International Conference on Microelectronics (MIEL 2021)
Niš September 12-14, 2021
This year, MIEL 2021 will be dedicated to
Professor Ninoslav Stojadinovic, founder of MIEL Conference.
Due to the unprecedented health, travel and social distance restrictions imposed in Serbia and all over the world as a result of the COVID-19 pandemic, all participants will be invited to join a virtual MIEL 2021.
Accepted papers will be published in the Proceedings of the MIEL 2021 Conference, and included in IEEE Xplore database, subject to regular registration of at least one of the authors before July 16th, 2021.
We are pleased to invite you, as an expert in the field of microelectronics, to submit a paper to MIEL 2021 Conference and to encourage colleagues to do it.
The deadline for the submission of two page-extended summaries (including figures, tables, and references) is May 7th, 2021.
Extended versions of selected papers from MIEL 2021 Conference will be published (after the regular review process) in:
Journal of Circuits, Systems and Computers
or
Facta Universitatis, Series: Electronics and Energetics
Looking forward to receiving your abstract for MIEL 2021 Conference, we remain with
Best regards,
Vojkan Davidović
Danijel Danković
Mar 19, 2021
[C4P] EuroSOI-ULIS 2021, September 1-3, 2021, Caen (F)
The Seventh Joint International EuroSOI and ULIS Conference
will be held in hybrid format in Caen, Normandy, France
from September 1 to September 3, 2021
After a virtual 2020 edition, if sanitary condition will permit, the 2021 EUROSOI-ULIS event will be held in hybrid format. The conference will be preceded on August 31, 2021 by "The Future of Nanoelectronics Devices and Systems Beyond Moore" Workshop.
The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference.
Original 2-page abstracts with illustrations will be accepted for review in pdf format.
Abstract submission is now open. The abstract submission deadline is Mai 17, 2021 Mai 31, 2021.
More information are provided on the Conference website:
https://eurosoiulis2021.sciencesconf.org
Papers in the following areas are solicited:
- Advanced SOI materials and structures; physical mechanisms and innovative SOI-like devices.
- New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
- Properties of ultra-thin films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ materials for switches and memory.
- Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, reliability, high frequency and memory applications.
- Alternative transistor architectures including FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
- New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
- CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration.
- Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
- Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
Confirmed Plenary Talks Speakers:
- Alexander Zaslavsky (Brown University, USA)
- Anne Vandooren (imec, Belgium)
- Frédéric Allibert (SOITEC, France)
- Jean-Michel Sallèse (EPFL, Switzerland)
- Sorin Cristoloveanu (IMEP Minatec, Grenoble, France)
- Sorin Voinigescu (University of Toronto, Canada)
The authors of the accepted contributions will be requested to provide a 4-page extended abstract which will be included in the Conference Technical Digest which will be published by IEEE and will be available online through IEEE Xplore. Outstanding papers will be invited for publication in a special issue of Solid-State Electronics.
The best paper award, renamed "The Androula Nassiopoulou Best Paper Award" in tribute to her, will be attributed by the SINANO Institute. The best poster award will be attributed by ELSEVIER.
We look forward to seeing you in Caen in 2021 ( https://en.normandie-tourisme.fr/unmissable-sites/caen/things-to-do/).
With best regards,
The EuroSOI-ULIS 2021 Organizing Committee
Note:
We are glad to inform you that 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Proceedings has been posted to the IEEE Xplore digital library
https://ieeexplore.ieee.org/xpl/conhome/9365069/proceeding
If you missed the last edition of EuroSOI-ULIS, do not miss the scientific articles published in the IEEE Xplore database! Many thanks to all authors and attendees for their essential contributions that endorsed EuroSOI ULIS'2020 as a successful virtual conference! Information on EuroSOI-ULIS'2020 virtual edition may be found in the IEEE EDS Newletter published in January 2021 (https://eds.ieee.org/publications/eds-newsletter ; pages 58-60)
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