Feb 18, 2021

[mos-ak] [Final Program] 1st Asia/South Pacific MOS-AK Workshop (Online) FEB. 25-26, 2021


Together with IEEE Young Professionals (at iitk.ac.in), the MOS-AK workshop online host as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the very first Asia/South Pacific MOS-AK Workshop which will be Virtual/Online event. Scheduled, 1st Asia/South Pacific MOS-AK Workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK workshop program is available online: 

Venue: Virtual/Online MOS-AK Workshop - FEB. 25-26, 2021
  • Day 1 (FEB.25) begins: 8:00 in Europe; 12:30 in India; 15:00 in China
  • Day 2 (FEB.26) begins: 8:00 in Europe; 12:30 in India;15:00 in China
Registered participant will receive online meeting invitation
(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications: Selected best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

W.Grabinski on the behalf of International MOS-AK Committee
WG18022021

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[linux] Conferences and Events

Python Web Conf - March 22 - 26, 2021
The 3rd annual Python Web Conf is a virtual event designed to promote best practices for hard web production problems. It features international experts presenting on 48 topics such as Django, Flask, Pyramid, Tornado, Plone, CI/CD, Containers, Serverless, REST APIs, web security, microservices, websockets, etc.

DrupalCon - April 12 - 16, 2021
The open source digital experience conference for Drupal.

Black Hat Asia 2021 - May 4-7, 2021
During this week, information security experts will teach interactive, online Trainings, innovative research will be presented at Briefings, the latest open-source tools will be showcased at Arsenal, and the Business Hall will feature top-tier security solutions and service providers, plus ample networking events and opportunities.
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Feb 17, 2021

#SIA has sent a letter to President Biden


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February 17, 2021 at 03:39PM
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Top #banks join #Linux and #opensource patent #protection group https://t.co/5d9B4a3ysh #semi https://t.co/XKGg4ioc9p


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February 17, 2021 at 03:21PM
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[Semiconductor Engineering by B.Moyer] #3D #FTJ stack for use in in-memory computing [Source: #IEDM/#Kioxia] https://t.co/oeNFCdXZTj #semi https://t.co/koAXAIKK03


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February 17, 2021 at 09:22AM
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[s3.i-micronews] NVIDIA Tesla P100 GPU with HBM2 2.5D & 3D Packaging https://t.co/1vs2c4qtvA #semi https://t.co/Z7vaqr8GGr


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February 17, 2021 at 09:14AM
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[papers] Compact/SPICE Modeling

[1] Peled, A, Amrani, O, Rosenwaks, Y.; DC and transient models of the MSET device; Int J Numer Model. 2021;e2869. https://doi.org/10.1002/jnm.2869
Abstract: As a multigate device, the multiple‐state electrostatically formed nanowire transistor (MSET) exhibits a rather complex characteristic on account of the coupling between each of its two adjacent terminals. The MSET has shown promise across a steadily growing range of applications and integrated circuit components. However, an analytical model of the MSET has not been formulated. The objective of this work was to develop practical DC and transient models of the MSET. The modeling approach comprises two stages: the first stage consists of a bottom‐up derivation of the I–V characteristics from the fundamental physical level using the physical processes within the device to derive equations that describe its steady‐state behavior; the second stage proposes a set of analytical equations more applicable to simulation environments. A transient model that considers device parasitic capacitance is also established. The models are validated against robust model simulations in TCAD Sentaurus and Cadence Virtuoso.

[2] Ciou, Jhang-Yan, Sourav De, Wallace Lin, Yao-Jen Lee, and Darsen Lu. "Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs." arXiv e-prints (2020): arXiv-2007.
Abstract: This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.
Fig: (a) Three-dimensional NC FinFET structure studied insimulation. (b) List of nominal device parameters used in TCAD simulation.

[3] Ahmed, Sheikh Z., Samiran Ganguly, Yuan Yuan, Jiyuan Zheng, Yaohua Tan, Joe C. Campbell, and Avik W. Ghosh. "A Physics Based Multiscale Compact Model of pin Avalanche Photodiodes." arXiv preprint arXiv:2102.04647 (2021).
Abstract: III-V material based digital alloy Avalanche Photodiodes (APDs) have recently been found to exhibit low noise similar to Silicon APDs. The III-V materials can be chosen to operate at any wavelength in the infrared spectrum. In this work, we present a physics-based SPICE compatible compact model for APDs built from parameters extracted from an Environment-Dependent Tight Binding (EDTB) model calibrated to ab-initio Density Functional Theory (DFT) and Monte Carlo (MC) methods. Using this approach, we can accurately capture the physical characteristics of these APDs in integrated photonics circuit simulations.
Fig: Schematic diagram of avalanche photodiode model and testbench used in the SPICE simulations.


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