[C4P] ICMTS: April 12 - 15, 2021

34th International Conference on Microelectronic Test Structures

ICMTS: April 12 - 15, 2021

Crowne Plaza Cleveland at Playhouse Square, Cleveland, OH, USA

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 34th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges. A Best Paper award will be presented by the Technical Program Committee. The IEEE Electron Devices Society is the co-sponsor, and all presented papers will be submitted for possible inclusion on IEEE Xplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, µ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number, and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favor of abstracts with high test structure content (including illustration) along with measurements and data analysis.

The abstract submission deadline is November 6, 2020.

Abstracts can be submitted via the ICMTS website http://www.icmts.net using the “Submit Abstract” link on the front page. Notice of paper acceptance will be sent to the selected authors by mid-January, 2020, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be March 17, 2021. 

Please join the ICMTS group at www.linkedin.com/groups/3804498, if you have in interest all things test structure related.

Details of the venue, hotel, registration, etc. will be posted at the ICMTS official web site. ICMTS is currently planned to be in person with the possibility of going virtual if necessary.

For further technical information, please contact the technical program chair:Chadwin Young, University of Texas at Dallas.

General Chair:

Brad Smith NXP Semiconductors

Technical Program Chair:

Chadwin Young University of Texas, Dallas

Tutorial Chair:

Matthew Rerecich Samsung Austin Semiconductor, LLC

Equipment Exhibition Chair:

Garrett Tranquillo Celadon Systems, Inc.

Local Arrangements:

Brad Smith NXP Semiconductors

ICMTS Steering Committee:

Asian Representative:

Satoshi Habu Keysight Technologies, Japan

European Representative:

Hans Tuinout NXP Semiconductors

USA Representative:

Bill Verzi Semiconductor Test Advisor

[online] PhD Thesis Colloquium of student Mr. Biswapriyo Das

FROM: Professor Santanu Mahapatra ( শান্তনু মহাপাত্র ) 

Nano Scale Device Research Laboratory
Department of Electronic Systems Engineering (formerly CEDT)
Indian Institute of Science Bangalore
Bangalore 560012 INDIA

Dear Colleagues, 
Hope you are in good health amid this pandemic.

I would like to invite you and your team members to the online thesis colloquium of my PhD student Mr. Biswapriyo Das. In our institute, it is mandatory for a PhD student to give an open colloquium for his research work just before the thesis submission. In pre-COVID time, it used to be a physical presentation, attended by the institute community. However, during this evolving pandemic we are conducting the colloquium online. It thus gives us opportunity to invite researchers across the globe who are working on the similar problems in device-modeling .

You may find the details of the talk below. Hope to see you and your group members on 19th October at 3PM IST. MS Teams Link:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_MjhmYzJiYjAtNzY2Zi00OGU5LWFhMzgtODQyYmJmNjAzYzhl%40thread.v2/0?context=%7b%22Tid%22%3a%226f15cd97-f6a7-41e3-b2c5-ad4193976476%22%2c%22Oid%22%3a%228c0cf3c3-0cab-451f-a745-7b29517ae80f%22%7d

Title:  Atom-to-circuit modeling strategy for 2D transistors

Abstract: Two-dimensional (2D) materials are now being considered as viable options for CMOS (complementary metal-oxide-semiconductor) technology extension due to their diverse electronic and opto-electronic properties. However, introduction of any new material in the process integration phase of technology development in semiconductor industry is an expensive and time-consuming affair. It is also a difficult task to select an appropriate 2D material from the plethora without assessing their performance at circuit level. Thus, first-principles-based multiscale models that enable systematic performance evaluation of emerging 2D materials at device and circuit levels solely from their crystallographic information is in great demand. In this thesis, such an atom-to-circuit modeling framework, addressing three different levels of abstraction (viz. material, device and circuit), has been demonstrated.
Firstly, the model was implemented for a van der Waal's heterostructure based all-2D metal-insulator-semiconductor field-effect transistor (MISFET), comprising of vertically stacked semi-metallic graphene, insulating hexagonal boron nitride (hBN) and semiconducting monolayer molybdenum disulphide (MoS­2). Our physics-based compact model demonstrates the effects of band gap opening in graphene due to its sublattice symmetry breaking interactions with underlying hBN layer. This apart, we have also studied the effects of semiconductor doping and the band gap variation of graphene at device and circuit levels. The model equations were thereafter implemented in a professional circuit simulator using its Verilog-A interface to facilitate design and simulation of integrated circuits.
Secondly, the scope of the proposed model was further extended to capture the non-quasi-static (NQS) effects in 2D transistors operating at very high frequencies, typically greater than its intrinsic cut-off frequency fT. Taking phosphorene as a prototypical example, a multiscale NQS model was developed for 2D transistors that can predict the channel-orientation-dependent high-frequency performance of devices and circuits solely from the crystallographic information of their constituent materials. The material-specific parameters obtained from density functional theory (DFT) calculations were used to develop a continuity equation based NQS model to gain insight into the high-frequency behaviours. It was found that channel orientation has strong impact on both the low and high frequency conductances, however it affects only the high-frequency component of capacitances. The model was then implemented in industry-standard circuit simulator using relaxation-time-approximation technique and simulations of analog and digital circuits were carried out to demonstrate its applicability for near cut-off frequency circuit operation.
Finally, the idea was also exercised for modeling novel quantum materials like 2D topological insulators (TI) and it was shown that the proposed analytical approach could be useful for developing compact models of topological insulator field effect transistors. A k. p Hamiltonian based continuum model was used to unveil the bandgap opening in the edge-state spectra of finite-width monolayer 1T' molybdenum disulphide (MoS2), molybdenum diselenide (MoSe2), tungsten disulphide (WS2) and tungsten diselenide (WSe­2). It was shown that the application of a perpendicular electric field effectuates a topological phase transition and it can simultaneously modulate the band gaps of both bulk and edge-states. The tuneable edge conductance, as obtained from the Landauer-Büttiker formalism, exhibits a monotonous increasing trend with applied electric field for deca-nanometer MoS­2, whereas the trend is opposite for other cases.

References:
[1] Das, B. and Mahapatra, S., "An atom-to-circuit modeling approach to all-2D metal-insulator-semiconductor field-effect transistors", npj 2D Mater Appl 2, 28 (2018).
[2] Das, B., Sen, D. and Mahapatra, S., "Tuneable quantum spin Hall states in confined 1Tʹ transition metal dichalcogenides", Sci Rep 10, 6670 (2020).
--------------------------------------------------------
Santanu Mahapatra ( শান্তনু মহাপাত্র )
Professor
Nano Scale Device Research Laboratory
Department of Electronic Systems Engineering (formerly CEDT)
Indian Institute of Science Bangalore
Bangalore 560012 INDIA

Adjunct Faculty IIIT-Allahabad

Phone: +91-80-2293-3090
Home Page: santanu.dese.iisc.ac.in
Lab Page: nsdrl.dese.iisc.ac.in

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj9c2QXCsyYYwLoDMZxRkZgyTy1ME83tDnYNMCqhSDBZLw%40mail.gmail.com.

[C4P] Special Issue "Smart Sensors for Wearable Applications" Keywords: Mobile health technology, Wearable technology, Smart sensors, Flexible and stretchable sensors, Optic sensors, Healthcare and wellness, IoT, Brain mapping https://t.co/EgX32M9eF2 #semi https://t.co/AwrzJ6qiYh

[C4P] Special Issue "Smart Sensors for Wearable Applications"
Keywords: Mobile health technology, Wearable technology, Smart sensors, Flexible and stretchable sensors, Optic sensors, Healthcare and wellness, IoT, Brain mappinghttps://t.co/EgX32M9eF2#semi pic.twitter.com/AwrzJ6qiYh

— Wladek Grabinski (@wladek60) October 13, 2020

---

from Twitter https://twitter.com/wladek60

October 13, 2020 at 05:15PM
via IFTTT

SOT-MRAM Startup Raises $11M to Achieve Scalability [EE Times Europe] https://t.co/TDMt5YKLOM #semi https://t.co/5Bic8ShFqg

SOT-MRAM Startup Raises $11M to Achieve Scalability [EE Times Europe] https://t.co/TDMt5YKLOM#semi pic.twitter.com/5Bic8ShFqg

— Wladek Grabinski (@wladek60) October 13, 2020

---

from Twitter https://twitter.com/wladek60

October 13, 2020 at 10:35AM
via IFTTT

[paper] TFETs for sensitive THz detection

I. Gayduchenko^1,2, S.G. Xu^3,4, G. Alymov¹, M. Moskotin^2,1, I. Tretyakov⁵, T. Taniguchi⁶, K.Watanabe⁷, G. Goltsman⁸, A.K. Geim^3,4, G. Fedorov^1,2, D. Svintsov¹, and D.A. Bandurin^3,1

Tunnel field-effect transistors for sensitive terahertz detection

arXiv:2010.03040 (2020)

¹Moscow Institute of Physics and Technology (National Research University), Dolgoprudny 141700, Russia
²Physics Department, Moscow Pedagogical State University, Moscow, 119435, Russia
³School of Physics, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom
⁴National Graphene Institute, University of Manchester, Manchester M13 9PL, United Kingdom
⁵Astro Space Center, Lebedev Physical Institute of the Russian Academy of Sciences, Moscow 117997, Russia
⁶International Center for Materials Nanoarchitectonics, National Institute of Material Science, Tsukuba 305-0044, Japan
⁷Research Center for Functional Materials, National Institute of Material Science, Tsukuba 305-0044, Japan
⁸National Research University Higher School of Economics, Moscow, 101000, Russia

Abstract: The rectification of high-frequency electromagnetic waves to direct currents is a crucial process for energy harvesting, beyond 5G wireless communications, ultra-fast science, and observational astronomy. As the radiation frequency is raised to the sub-terahertz (THz) domain, efficient ac-to-dc conversion by conventional electronics becomes increasingly challenging and requires alternative rectification protocols. Here we address this challenge by tunnel field-effect transistors made of dual-gated bilayer graphene (BLG). Taking advantage of BLG’s electrically tunable band structure, we create a lateral tunnel junction and couple it to a broadband antenna exposed to THz radiation. The incoming radiation is then down-converted by strongly non-linear interband tunneling mechanisms, resulting in exceptionally high-responsivity (exceeding 3kV/W) and low-noise (0.2pW/Hz−−−√)  detection at cryogenic temperatures. We demonstrate how the switching from intraband Ohmic to interband tunneling regime within a single detector can raise its responsivity by one order of magnitude, in agreement with the developed theory. Our work demonstrates an unexpected application of interband tunnel transistors for high-frequency detection and reveals bilayer graphene as one of the most promising platforms therefor.

Fig: Overview of THz detectors. NEP for THz detectors of various types plotted against the temperature at which they operate. Vertical error bars represent the spread of the detectors’ performance over the frequency range 0.1−2 THz. Horizontal error bars show the temperature range at which the detectors operate.  

Acknowledgements: This work was supported by the Russian Foundation for Basic Research within Grants No. 18-37-20058 and No. 18-29-20116. Experimental work of IG (photoresponse measurements) was supported by the Russian Foundation for Basic Research (grant 19-32-80028). We acknowledge support of the Russian Science Foundation grant No. 19-72-10156 (NEP analyses) and grant No.17-72-30036 (transport measurements). The work of GA and DS (theory of THz detection) was supported by grant # 16-19-10557 of the Russian Scientific Foundation. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, Grant Number JPMXP0112101001, JSPS KAKENHI Grant Number JP20H00354 and the CREST(JPMJCR15F3), JST. The authors thank A. Lisauskas, W. Knap, A. I. Berdyugin and M.S. Shur for helpful discussions.

[paper] Compact Modeling of GaN HEMTs

Y. Chen et al., "Compact Modeling of THZ Photomixer Made from GaN HEMT," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 484-489, doi: 10.1109/AEECA49918.2020.9213681.

Y. Chen et al., "A Surface Potential Based Compact Model for GaN HEMT I-V and CV Simulation," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 490-495, doi: 10.1109/AEECA49918.2020.9213674.

A. Zhang et al., "Compact Modeling of Capacitance Components for GaN HEMTs," 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA), Dalian, China, 2020, pp. 505-511, doi: 10.1109/AEECA49918.2020.9213571.

FIG: Simplified GaN HEMT Structure

[chapter] Low-Voltage Analog IC Design

Deepika Gupta¹

Low-Voltage Analog Integrated Circuit Design

Nanoscale VLSI. Book series (ESIEE) (2020) pp 3-22

DOI: 10.1007/978-981-15-7937-0_1

¹Department of Electronics and Communication Engineering, IIIT Naya Raipur, India

Abstract: In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply VDD is reducing but the threshold voltage VT is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in VDD to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques. The charge-based EKV model can be a very suitable example of a MOS simulation model to be used in all inversion regions of transistor operations [Enz 2017]. In EKV model, the smallest number of core parameters is needed for the accurate behavioral modeling of transistor. Particularly, charge-based EKV model is beneficial for the analysis of analog circuits because it allows the analysis with simple calculations over different inversion regions. Hence, developing new device simulation models specific for analog circuit design is crucial.

Fig: Vth and Vdd scaling trend vs. Leff  [Zhao 2006]

References:

[Enz 2018] Enz C, Chicco F, Pezzotta A (2017) Nanoscale MOSFET modeling-part 1: the simplified EKV model for the design of low-power analog circuits. IEEE Solid-State Circuits Magazine 9(3):26–35

[Zhao 2006] Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans Electron Devices 53(11):2816–2823