Jun 2, 2020

[paper] In-memory hyperdimensional computing

In-memory hyperdimensional computing
Geethan Karunaratne, Manuel Le Gallo, Giovanni Cherubini, Luca Benini, Abbas Rahimi
and Abu Sebastian 
Nature Electronics (2020)
DOI: 10.1038/s41928-020-0410-3

Abstract: Hyperdimensional computing is an emerging computational framework that takes inspiration from attributes of neuronal circuits including hyperdimensionality, fully distributed holographic representation and (pseudo)randomness. When employed for machine learning tasks, such as learning and classification, the framework involves manipulation and comparison of large patterns within memory. A key attribute of hyperdimensional computing is its robustness to the imperfections associated with the computational substrates on which it is implemented. It is therefore particularly amenable to emerging non-von Neumann approaches such as in-memory computing, where the physical attributes of nanoscale memristive devices are exploited to perform computation. Here, we report a complete in-memory hyperdimensional computing system in which all operations are implemented on two memristive crossbar engines together with peripheral digital complementary metal–oxide–semiconductor (CMOS) circuits. Our approach can achieve a near-optimum trade-off between design complexity and classification accuracy based on three prototypical hyperdimensional computing-related learning tasks: language classification, news classification and hand gesture recognition from electromyography signals. Experiments using 760,000 phase-change memory devices performing analog in-memory computing achieve comparable accuracies to software implementations.
Fig.: The concept of in-memory hyperdimensional computing.

Acknowledgements: This work was supported in part by the European Research Council through the European Union’s Horizon 2020 Research and Innovation Programme under grant no. 682675 and in part by the European Union’s Horizon 2020 Research and Innovation Programme through the project MNEMOSENE under grant no. 780215.


Jun 1, 2020

[paper] Device Scaling for 3-nm Node and Beyond

Opportunities in Device Scaling for 3-nm Node and Beyond:
FinFET Versus GAA-FET Versus UFET
U. K. Das and T. K. Bhattacharyya
in IEEE TED, vol. 67, no. 6, pp. 2633-2638, June 2020, 
doi: 10.1109/TED.2020.2987139

Abstract: The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (Ieff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in Ieff. Therefore, to enable future devices, we explored electrostatics and Ieff in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced TCAD device simulator.

Fig: Transistor architectures for future technologies. (a) FinFET device
(in {001} substrate plane, and sidewalls are in {110} planes) with crosssectional
fin channel (5 nm thin). (b) Fin is changed into a four-stacked
GAA-LNWs. (c) GAA- LNS having 20-nm width (W). (d) UFET structure.

Acknowledgment: The authors would like to thank Dr. Bidhan Pramanik, IIT Goa, India, Dr. KB Jinesh, IIST, Trivandrum, India, and Dr. Geert Eneman, IMEC, Leuven, Belgium, for their valuable technical support.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9078841&isnumber=9098120

#US putting $37bn into #semiconductors. The aim is to match #China in its state investment in semiconductors. https://t.co/jJ6adDEiSE #paper https://t.co/pHv5mcyi6m


from Twitter https://twitter.com/wladek60

June 01, 2020 at 08:59AM
via IFTTT

May 31, 2020

#DISLIN Graphics Library to plot S- and Y-parameters on Smith Charts, and to create arbitrary Cartesian plots of S-parameter data along with Polar plots of radiation patterns. https://t.co/Fj7CEHywUv #paper https://t.co/A0cRlYw3uH


from Twitter https://twitter.com/wladek60

May 31, 2020 at 09:55PM
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[paper] ReRAM: History, Status, and Future

ReRAM: History, Status, and Future
Y. Chen, Member, IEEE
Western Digital Corporation, Milpitas, CA
in IEEE TED, vol. 67, no. 4, pp. 1420-1433, April 2020
doi: 10.1109/TED.2019.2961505.


Abstract: This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed. 
Fig: General category of resistive switching memory technologies
with ReRAM highlighted as the review focus

Acknowledgment: Sincere acknowledgment to people who ever contribute to ReRAM technology development and understanding.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8961211&isnumber=9046113

May 29, 2020

What Rhymes With #SPICE And Simulates Huge Circuits? https://t.co/RGyWLKVDzS #paper https://t.co/trzKPb8w2A


from Twitter https://twitter.com/wladek60

May 29, 2020 at 03:58PM
via IFTTT

Open PhD and Post-Doc positions at BIU

Dr. Adam Teman is a tenure track Senior Lecturer at Bar-Ilan University in Ramat Gan, Israel and a leading member of the Emerging Nanoscaled Circuits and Systems (EnICS) Labs at BIU. Dr.Temen is also among  the Woolf Foundation's 2020 Krill Award winners for young Israeli researchers. Dr.Teman is looking now for candidates for PhD and Post-Doc positions. Please contact him at adam.teman@biu.ac.il 

Dr. Adam Teman Research IC Tapeouts
  • 2019 - SoC2 System-on-Chip (TSMC 16FFC)
  • 2018 - Kwak Gain Cell eDRAM T(Samsung 28nm FD-SOI)
  • 2017 - Martini Gain Cell eDRAM (ST 28nm FD-SOI)
  • 2016 - BEER Gain Cell eDRAM (ST 28nm FD-SOI)
  • 2016 - DAFNA Gain Cell eDRAM (TSMC 28nm)