IEDM took place last week with: * Tutorials on Saturday * Two parallel short courses on Sunday * Plenary session on Monday morning * Press luncheon on Monday * Then a dozen sessions running in parallel https://t.co/hdrySfWNHf #paper https://t.co/0GxwGRMy0A

IEDM took place last week with:
* Tutorials on Saturday
* Two parallel short courses on Sunday
* Plenary session on Monday morning
* Press luncheon on Monday
* Then a dozen sessions running in parallelhttps://t.co/hdrySfWNHf #paper pic.twitter.com/0GxwGRMy0A

— Wladek Grabinski (@wladek60) December 19, 2019

from Twitter https://twitter.com/wladek60

December 19, 2019 at 03:48PM
via IFTTT

IRPhE 2020 Aghveran, Armenia

International Conference on Microwave & THz Technologies,

Wireless Communications and OptoElectronics

September 23-25, 2020, Aghveran, Armenia

IRPhE 2020 Call for Papers

The aim of the IRPhE’ 2020 Conference is to provide an open forum for the presentation and discussion of current research in Microwave and THz technologies, wireless communications, alternative electronic devices, photonics and its applications.

The main topics of the conference are and not limited to:

• Microwave devices, antennas, propagation and remote sensing
• THz technique, spectroscopy and applications
• Alternative semiconductor and dielectric materials, electronic devices
• Wireless communications and related information technologies
• Microwave photonics

For further information visit the website: http://www.irphe.am/?q=conference

Submission Information

Original one page abstracts will be accepted for review in Word and PDF formats.The accepted abstracts will be published in an abstract book and distributed during the conference.

All the authors who have presented their work at the conference will be invited to submit 4-page follow-up papers for publication special IJHSES issue on the "Microwave and THz technologies"

Abstracts must be submitted via email: science@irphe.am.

Intel’s Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm; It’s worth also pointing out, based on the title of this slide, that #Intel still believes in #Moore’s Law. Just don’t ask how much it’ll cost. https://t.co/VIwrSoWEgB #paper https://t.co/LorF5xyHnT

Intel’s Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm; It’s worth also pointing out, based on the title of this slide, that #Intel still believes in #Moore’s Law. Just don’t ask how much it’ll cost. https://t.co/VIwrSoWEgB #paper pic.twitter.com/LorF5xyHnT

— Wladek Grabinski (@wladek60) December 17, 2019

from Twitter https://twitter.com/wladek60

December 17, 2019 at 12:03PM
via IFTTT

#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb https://t.co/xxTqg2iAMI

#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL
doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb pic.twitter.com/xxTqg2iAMI

— Wladek Grabinski (@wladek60) December 16, 2019

from Twitter https://twitter.com/wladek60

December 16, 2019 at 02:22PM
via IFTTT

The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper https://t.co/dkTuVHseGP

The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper pic.twitter.com/dkTuVHseGP

— Wladek Grabinski (@wladek60) December 16, 2019

from Twitter https://twitter.com/wladek60

December 16, 2019 at 11:13AM
via IFTTT

The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, now https://t.co/0iDmBChDVm https://t.co/BTBAbPm7aN

The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, nowhttps://t.co/0iDmBChDVm pic.twitter.com/BTBAbPm7aN

— Wladek Grabinski (@wladek60) December 4, 2019

from Twitter https://twitter.com/wladek60

December 04, 2019 at 03:23PM
via IFTTT

[mos-ak] [Final Program] 12th International MOS-AK Workshop; Silicon Valley, Dec.11 2019

12th International MOS-AK Workshop

(co-located with the IEDM and Q4 CMC Meetings)

Silicon Valley, December 11, 2019

<http://www.mos-ak.org/silicon_valley_2019/>

Together with Silvaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 12th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. 

The MOS-AK workshop program is available online:

<http://www.mos-ak.org/silicon_valley_2019/>

Venue:

Silvaco 

2811 Mission College Blvd., 6th Floor 

Santa Clara, CA 95054

Online Registration is still open

(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special Solid State Electronics issue on compact modeling 

W.Grabinski on the behalf of International MOS-AK Committee

WG02122019

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