[Report] 2nd Latin America MOS-AK Workshop at LAEDC

Recently the 2nd Latin America MOS-AK Workshop at LAEDC was reported in IEEE EDS Newsletter, July 2020 Vol. 27, No. 3 ISSN: 1074 1879 by Lluis Marsal and Benjamin Iñiguez:

The 2nd Latin American edition of the MOS-AK Workshop on Compact Modeling was held at LAEDC in San Jose, Costa Rica, was held in conjunction with the Latin American Symposium on Circuits and Systems (LASCAS 2020).. It was chaired by Prof. Benjamin Iñiguez (Universitat Rovira I Virgili, Tarragona, Spain). It included five talks. Prof. Antonio Cerdeira (CINVESTAV, Mexico) presented an "Analytical Current Voltage Model for Double Gate a-IGZO TFTs with Symmetric Structure." Prof. Alexander Kloes (THM, Giessen, Germany) addressed "Approaches for Analytical (Compact) Modeling of Tunneling Currents in MOS Transistors." Prof. Jean-Michel Sallese (EPFL, Switzerland) gave a talk about "Modeling the Junctionless Ion Sensitive Field Effect Transistor" Prof. Gilson Wirth (UFRGS, Porto Alegre, Brazil) targeted "The area scaling of charge trap induced time-dependent variability." Finally, Prof. Benjamin Iñiguez (URV, Tarragona, Spain) talked about "Characterization and modeling of 1/f noise in organic and IGZO TFTs". Over 70 academics, professionals and students attended these events and enjoyed the discussions with the speakers. 

Visit also <http://www.mos-ak.org/costa_rica_2020/>

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[mos-ak] Fwd: ESSCIRC ESSDERC 2020 | before going on holiday

Are you all set for your well deserved summer holiday? Before you go, have a look at ESSCIRC ESSDERC 2020 Educationals and do not forget to register! 1. TUTORIAL | Quantum Computing: Myth or Reality? 2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems 3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems 4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system) 5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN) 6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications 7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions 8. WORKSHOP | Ab-initio simulations supporting new materials & process developments 9. WORKSHOP | RISC-V cooking session 10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data 11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities 12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization 13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future REGISTER NOW! JOIN NOW OUR  ESSCIRC – ESSDERC LinkedIn group! ORGANIZING COMMITTEE Thomas Ernst (CEA-LETI, FR), General co-chair Dominique Thomas (STMicroelectronics, FR), General co-chair François Andrieu (CEA-LETI, FR), ESSDERC TPC Chair Maud Vinet (CEA-LETI, FR), ESSDERC TPC co-Chair Andreia Cathelin (STMicrolectronics, FR), ESSCIRC TPC Chair Sylvain Clerc (STMicrolectronics, FR),  ESSCIRC TPC co-Chair LOCAL EXECUTIVE SECRETARIAT Sandra Barbier (CEA-LETI, FR) | sandra.barbier@cea.fr ORGANIZING SECRETARIAT Sistema Congressi s.r.l. | essxxrc@sistemacongressi.com  ORGANIZERS TECHNICAL SPONSORSHIP FINANCIAL SPONSORSHIP WELCOME OUR DIAMOND SPONSOR! View this email in your browser Copyright © 2020 Sistema Congressi s.r.l., All rights reserved. You are receiving this email because you attended or expressed interest in ESSCIRC-ESSDERC events, or because you are involved in similar fields of research Our mailing address is: Sistema Congressi s.r.l. via Trieste, 26 Padova, PD 35121 Italy Add us to your address book Want to change how you receive these emails? You can update your preferences or unsubscribe from this list.

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Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15 #semi https://t.co/W5DgoT4Kul

Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15#semi pic.twitter.com/W5DgoT4Kul

— Wladek Grabinski (@wladek60) July 30, 2020

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from Twitter https://twitter.com/wladek60

July 30, 2020 at 11:22AM
via IFTTT

[paper] Compact Modeling of IGBT

Y. Miyaoku, A. Tone, K. Matsuura, M. Miura-Mattausch, H. J. Mattausch, and *D. Ikoma

Compact Modeling of IGBT Charging/Discharging

for Accurate Switching Prediction

IEEE J-EDS,  DOI:10.1109/jeds.2020.3008919 

Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

*Denso Corp., Aichi, Japan

Abstract: The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.

Fig: Studied IGBT structure with indicated current flows

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.