Possible VTH Variation Sources

with 16 nm FinFET devices, the nature of the VTH variation changes.  On planar CMOS, random dopant fluctuations (RDFs) had the biggest influence. 

Possible VTH Variations

Ideal FinFETs have no doping, and therefore no RDFs.  However, this only works for low voltage operation.  We also need high-speed devices, which requires multiple threshold voltages (Vth's).  For FinFETs, this requires doping leading to RDF variation.  

[read more at DeepChip ...]

New IJNM Paper

 
Open-source circuit simulation tools for RF compact semiconductor device modelling (Invited Paper)
 
Wladek Grabinski (Editor), Mike Brinson, Paolo Nenzi, Francesco Lannutti, Nikolaos Makris, Angelos Antonopoulos and Matthias Bucher
 
Keywords:
CAD; GNU; Qucs; QucsStudio; ngspice; compact modelling; EKV3; RF; MOSFET; Verilog-A
 
Article first published online: 18 MAR 2014 DOI: 10.1002/jnm.1973

website http://www.tcad.com is up and running

The www.tcad.com website promoting open source Technology Computer Aided Design and posting related news is up and running. Among other news there is also update of the DEVSIM Open Source TCAD Simulator which is available for download at SourceForge, now.  Packages are available for:

• Mac OS X Mavericks
• Red Hat 6.5
• Ubuntu 12.04

For more information about the project, including source code availability, please visit DEVSIM webpage. Additional resource are also available at the TCADCentral 

[source]

Free And Open Source Simulator Software For Engineers

Free And Open Source Simulator Software For Engineers

0. Qucs
Download Link: http://qucs.sourceforge.net/download.html
Supported OS: Windows, Linux, Mac OSX
License:  Qucs is released under the GPL license and so it is free for free programmers and users !
Qucs stands for Quite Universal Circuit Simulator. So far Qucs is not yet finished, but it is already packed with features. Take a look at the screenshots to get a feel for what it can do.

1. CEDAR
Download Link: http://sourceforge.net/projects/cedarlogic/files/latest/download
Supported OS: Windows
License: Freeware
CEDAR LS is an interactive digital logic simulator to be used for teaching of logic design or testing simple digital designs. It features both low-level logic gates as well as high-level components, including registers and a Z80 microprocessor emulater

2. Logisim
Download Link: http://sourceforge.net/projects/circuit/files/latest/download
Supported OS: Windows, Linux
License: Freeware
Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits.

3. FreeMat
Download Link: http://sourceforge.net/projects/freemat/files/latest/download?source=files
Supported OS: Windows, Linux
License: GPL
FreeMat is a free environment for rapid engineering and scientific prototyping and data processing. It is similar to commercial systems such as MATLAB from Mathworks, and IDL from Research Systems, but is Open Source. FreeMat is available under the GPL license.

4. Logic Gate Simulator
Download Link: http://sourceforge.net/projects/gatesim/files/latest/download
Supported OS: Windows
License: GPL
Logic Gate Simulator is an open-source tool for experimenting with and learning about logic gates. Features include drag-and-drop gate layout and wiring, and user created "integrated circuits".

5. Maxima
Download Link: http://sourceforge.net/projects/maxima/files/latest/download?source=recommended
Supported OS: Windows
License: GPL
Maxima is a fairly complete computer algebra system written in Common Lisp with an emphasis on symbolic computation.

6. Ngspice
Download Link: http://sourceforge.net/project/showfiles.php?group_id=38962
Supported OS: Windows, Linux
License: GPL
Ngspice is a mixed-level/mixed-signal circuit simulator. Its code is based on three open source software packages: Spice3f5, Cider1b1 and Xspice. Ngspice is part of gEDA project, a full GPL'd suite of Electronic Design Automation tools.

7. Qfsm
Download Link: http://sourceforge.net/projects/qfsm/files/latest/download
Supported OS: Windows, Linux
License: GPL
A graphical tool for designing finite state machines

8. QSapecNG
Download Link: http://sourceforge.net/projects/qsapecng/files/latest/download?source=directory
Supported OS: Windows
License: GPL
QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.

[source for 1-8]

SISPAD2014: 2nd Call for Papers

Second Call for Papers

SISPAD2014

September 9 – 11, 2014

Workshop, September 8, 2014

Mielparque Yokohama, Yokohama, JAPAN

Co-sponsored by Japan Society of Applied Physics Technical 

Co-sponsored by IEEE Electron Devices Society

This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Topics:

• Modeling and simulation of all sorts of semiconductor devices, including FinFETs, ultra-thin SOI devices, emerging memory devices, optoelectronic devices, TFTs, sensors, power electronic device, widegap semiconductor devices, spintronic devices, tunnel FETs, SETs, carbon-based nanodevices, organic electronic devices, and bioelectronic devices
• Modeling and simulation of all sorts of semiconductor processes, including first-principles material design and growth simulation of nano-scale fabrication
• Fundamental aspects of device modeling and simulation, including quantum transport, thermal transport, fluctuation, noise, and reliability
• Compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
• Process/device/circuit co-simulation in context with system design and verification
• Equipment, topography, lithography modeling
• Interconnect modeling, including noise and parasitic effects
• Numerical methods and algorithms, including grid generation, user-interface, and visualization
• Metrology for the modeling of semiconductor devices and processes

Plenary Speakers:

• Augusto Benvenuti, Micron Technology,
  “Current status and future prospects of non-volatile memory modeling”
• Massimo V. Fischetti, University of Texas at Dallas,
  “Physics of electronic transport in low-dimensionality materials for future FETs”
• Kimimori Hamada, Toyota Motor Corporation,
  “TCAD challenge on development of power semiconductor devices for automotive applications”

Invited Speakers:

• Mario Ancona, Naval Research Laboratory,
  “Nonlinear thermoelectroelastic simulation of III-N devices”
• Asen Asenov, University of Glasgow,
  “Progress in the simulation of time dependent statistical variability in nano CMOS transistors”
• Jean-Pierre Colinge, Taiwan Semiconductor Manufacturing Company,
  “Nanowire transistors: pushing Moore's law to the limit”
• Tibor Grasser, Vienna University of Technology,
  “Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI”
• Kohji Mitsubayashi, Tokyo Medical and Dental University,
  “Novel biosensing devices for medical applications”
• Christian Sandow, Infineon Technologies,
  “Exploring the limits of the safe operation area of power semiconductor devices”
• Mark Stettler, Intel Corporation,
  “Device and process modeling: 20 years at Intel's other fab”

Workshops:

Two companion workshops will run concurrently prior to the start of the conference on Monday September 8, 2014:

• Compact Modeling "Enabling Better Insight of Device Features"
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Carrier Transport in Nano-Transistors: Theory and Experiments
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Abstract Submission: 

Authors are invited to submit a two-page abstract (A4 or 22×28cm) including figures. Full submission information is available at the ing web page: <https://sites.google.com/site/sispad2014/>. Authors of accepted papers will be notified by May 15, 2014. Camera-ready copy of a four-page manuscript will be required from the authors for inclusion in the Conference Proceedings by June 30, 2014.

Deadline for submission of abstract: March 31, 2014