[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] Device for the Detection and Quantification of Exosomes

Diego Barrettino1, Christoph Zumbühl1, Raphael Kummer1, Markus Thalmann1, Carolina Balbi2, Giuseppe Vassalli2, Rosane Moura Dos Santos3 and Jean-Michel Sallese3

Low-Cost Portable Medical Device for the Detection and Quantification of Exosomes

2023 IEEE SENSORS, Vienna, Austria, 2023, pp. 1-4,

doi: 10.1109/SENSORS56945.2023.10325271. 

1 Lucerne University of Applied Sciences and Arts (HSLU), Institute of Electrical Engineering, CH- 6048 Horw, Switzerland
2 Istituto Cardiocentro Ticino, Via Tesserete 48, CH-6900 Lugano, Switzerland
3 Swiss Federal Institute of Technology Lausanne (EPFL), EPFL SCI STI EDLAB, Station 11, CH-1015 Lausanne, Switzerland

Abstract: The design, fabrication and testing of a low-cost portable medical device for the detection and quantification of exosomes is presented in this paper. The portable medical device comprises a sensor array that can detect the presence of exosomes and quantify its concentration, a microfluidic device that handles the human serum containing the exosomes, and all the necessary readout and control electronics. Measurement results performed with exosomes showed that the portable medical device can detect exosomes with a concentration of 2.5x108 /µL thus paving the way to a wide range of diagnostic applications.

Fig. Exosome immobilized on top of the functionalized (antibody CD63 +protein G
+ polydopamine + graphene oxide) JLFET biosensor and tagged with a gold (Au) nanoparticle attached to an exosome biomarker (antibody CD31)

[C4P] 50th ESSERC, Sept. 9-12. 2024, Bruges (BE)

CALL FOR PAPERS

https://www.esserc2024.org/papers

The aim of ESSERC (European Solid-State Electronics Conference) is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. It is a continuation of the past ESSDERC-ESSCIRC conferences. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. 

ESSERC is governed by a Steering Committee and consists of Plenary Keynote Presentations, invited papers and session on technology, circuits and joint papers bridging both device and circuit communities, respectively. 

PAPERS SUBMISSION DEADLINE: APRIL 5, 2024

Papers submitted for review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the art
• Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 24 May 2024.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one (co-)author is required to register for the Conference (one registration one paper policy). Registration fees and deadlines will be soon available

CONFERENCE TRACKS (although not limited, papers are solicited for the following main topics):

1. Advanced Technology, Process and Materials
2. Analog, Power and RF Devices
3. Compact Modeling and Process/Device Simulation
   
   TCAD and advanced simulation techniques and studies, compact/ SPICE modeling of electronic, optical, organic, emerging, and hybrid devices and their IC implementation and interconnection. Verilog-A models of semiconductor devices (including bio/ med sensors, MEMS, microwave, RF, high voltage and power, emerging technologies, and novel devices), parameter extraction, reliability and variability, performance evaluation and open-source benchmarking/implementation methodologies. Modeling of interactions between process, device and circuit design, design/technology co-optimization, foundry/fabless interface strategies. Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation, and 2D/3D integration. Simulations of material properties and fabrication processes. Advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport). Mechanical and/or electro-thermal modeling and simulation. Simulations of reliability aspects of materials and devices.
4. Analog Circuits
5. Data Converters
6. RF & mm-Wave Circuits
7. Frequency Generation Circuits
8. Digital Circuits & Systems
9. Power Management
10. Wireless Systems
11. Wireline and Optical Circuits and Systems
12. Emerging Computing Devices and Circuits
13. Architectures and Circuits for AI and ML
14. Devices & Circuits for Sensors, Imagers and Displays

WHY BRUGES?

Bruges is a place that lives and breathes history. Visiting this historic city means travelling back in time to the Middle Ages. It is both magical and authentic. Brugge in medieval times was known as a commercial metropolis in the heart of Europe. 

Bruges is one of Europe’s best-preserved cities, evidenced by the fact that its historic city center has been designated an UNESCO World Heritage Site. The iconic spires of its cathedral and bell tower, its cobbled streets, winding canals and whitewashed façades are almost painfully picturesque.

In the 15th century, Brugge was the cradle of the Flemish Primitives and a center of patronage and painting development for artists such as Jan van Eyck and Hans Memling. Many of their works were exported and influenced painting styles all over Europe. Exceptionally important collections have remained in the city until today. Travelers from all over the world are coming to Belgium to visit Bruges.

[mos-ak] [Final Program] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

16th International MOS-AK Workshop

Silicon Valley, December 13, 2023

Together with Keysight Technologies team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 16th International MOS-AK Workshop in Silicon Valley.

Scheduled 16th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in Open Access PDKs.

The MOS-AK workshop program is available online:

<https://www.mos-ak.org/silicon_valley_2023/>

Venue:

Keysight Technologies

5301 Stevens Creek Boulevard

Santa Clara, CA 95051

Online Free Registration; 

any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK Committee

WG291023

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[paper] Noise modeling for cryogenic applications

Giovani Britton^1,2, Salvador Mir², Estelle Lauga-Larroze², Benjamin Dormieu¹, Quentin Berlingard^3,4, Mickael Casse³ and Philippe Galy¹

Noise modeling using look-up tables and DC measurements for cryogenic applications.

VLSI-SoC 2023 - 31st IFIP/IEEE International Conference on Very Large Scale Integration,

Oct 2023, Sharjah, United Arab Emirates.

DOI: 10.1109/VLSI-SoC57769.2023.10321896
hal-04305746

1STMicroelectronics, Crolles, France

2Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA

3Univ. Grenoble Alpes, CEA, LETI

4Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC

Abstract : There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a LookUp Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.

Fig : Measurement data and EKV or ACM generated parameters are added

to the LUT generated by the interface between EDA tools

Acknowledgments : This work was supported by the French program Conventions Industrielles de Formation par la Recherche (CIFRE) and Labex MINOS of French program ANR-10-LABX-55-01.