Sep 27, 2022

[online] Consultation workshop "Chips for Europe" Initiative

Consultation workshop "Chips for Europe" Initiative
Shaping Europe's digital future

As part of the ongoing consultation on the upcoming implementation of the "Chips for Europe" Initiative, as foreseen within Pillar 1 of the proposed Chips Act, we are organising a virtual workshop on Thursday 29th September 2022. Here we will be presenting the Commission's ideas on future pilot lines and a design platform, key components of the Commission's strategy to strengthen the semiconductor ecosystem in Europe and accelerate the process from the lab to the fab. 

The workshop will be split into two parts:
10:00 – 12:30 CET: design platform and its implementation
14:00 – 16:30 CET: pilot lines and their implementation
The agenda will include an opportunity for an exchange of views with stakeholders.

Those interested in joining are invited to register.

Sep 25, 2022

Hermann K. Gummel Obituary

as posted <https://ieee-ceda.org/post/hermann-k-gummel-obituary>

Beloved Hermann Gummel passed away on Monday, 5 September at 99 years old, surrounded by his ‘dearly ones’. Hermann was born on 6 July 1923 in Hannover, Germany to Hans and Charlotte Gummel, the middle brother of an older sister, Bärbel, and younger brother, Achi. After graduating high school, Herman was enlisted as a radio operator for the German army in World War II. He was wounded and taken prisoner during the Normandy Landing (DDay) and ultimately sent to a hospital in Scotland. Throughout his life, Hermann was deeply grateful for the compassionate care of the doctors and staff there, who saved his leg from amputation.

Hermann’s intellectual aptitude and interest in academia would define the trajectory of his life. After the war, he enrolled in the University of Marburg as a wounded veteran, where he fell in love with, and later married, his wife Erika Reich. They were married for 64 years before her passing in 2016.

In addition to love, academia also took Hermann to new land. Hermann was awarded a Fullbright scholarship to Syracuse University, marking the beginning of a new life that he and Erica would forge together in the United States. Hermann obtained his doctorate in Physics, during which he also became a father for the first time to his daughter Monica in 1953. Hermann and Erica’s second daughter, Margaret was born five years later in 1958.

After completing his Doctorate, the family moved to Plainfield, NJ in 1957 and Hermann began a lifelong career working at Bell Laboratories. Hermann worked as a Director at “Mother Bell” for 30 years, then as a consultant for an additional 10+ years after his “retirement”. Throughout this time, the family lived in North Plainfield (1960-1976), then Berkeley Heights (1976-2005), and finally, at the Cedar Crest Senior Living Community in northern New Jersey.

Within the scientific community, Hermann is considered a pioneer in the semiconductor industry, leaving behind a distinguished legacy in the field of design technology for integrated electronics. He was a scientific mentor, leader, and visionary for many in the field. Awarded the prestigious Phil Kaufman award and known for the ‘Gummel Number’, the Gummel-Poon Model, and numerous other technical achievements. Within his family, he continues to be simply and lovingly, “Dad” and “Opa”.

Hermann is survived and loved by both his children, Monica and Margi, his grandchildren, Tracy and Pammy, as well as his great-grandchildren, Marco and Nico. The scientific community will remember Hermann for his technical contributions. His loved ones will remember him for his integrity, boundless intellectual curiosity and discipline, his loyalty, and a heart that was endlessly grateful for the life he lived and those he loved.

Sep 23, 2022

'Moore's Law Is Dead,' Says Nvidia CEO Says - Slashdot https://t.co/AJY0GBJOpv #semi https://t.co/QFRTwAud1D



from Twitter https://twitter.com/wladek60

September 23, 2022 at 10:07PM
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Sep 21, 2022

Distinguished Lecturer Program on "FOSS TCAD/EDA Tools SPICE and Verilog-A Modeling Flow"

We are glad to inform you that the IEEE Student Branch MNIT Jaipur in association with IEEE EDS Student Branch Chapter MNIT Jaipur is organizing an invited talk on ''FOSS TCAD/EDA Tools SPICE and Verilog-A Modeling Flow''  by Dr Wladek Grabinski, R&D SPICE Manager, MOS-AK (EU)

There is no registration fee, however prior registration is required. This invited talk will be held in online mode.

E-certificate will be provided to all registered participants.

Title: ''FOSS TCAD/EDA Tools SPICE and Verilog-A Modeling Flow"

Abstract:Compact/SPICE models of circuit elements (passive, active, MEMS, RF, Microwave, Photonics) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along the complete technology/design tool chain from nanascaled technology processes; thru the compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Application and use of these tools for advanced IC design (e.g. analog/RF, Microwave, Photonics applications) directly depends on the quality of the compact model implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the semiconductor device level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

Registration Link: 

https://forms.gle/xnkEo2i92UzdjK5PA

Joining Link:

http://meet.google.com/cpd-mopg-eea

Date: 22nd September 2022

Time: 03:00-04:00 PM IST

We are looking forward to active participation from your side.


Girdhar Gopal

Research Scholar, MNIT Jaipur

Chair, Student Branch Chapter 

MNIT, Jaipur

Sep 20, 2022

[https://t.co/ESTgq7BilY] Automated SoC, Mixed-Signal Design using OpenROAD and OpenFASoC #RTL #GDSII #OpenSource #semi https://t.co/F1wjbbSWnO



from Twitter https://twitter.com/wladek60

September 20, 2022 at 02:59PM
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