Mar 21, 2022

Andy Grove: Refugee, Tech Pioneer And Immigrant Entrepreneur



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Mar 18, 2022

Tso-Ping Ma (1945−2021)



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Transistor qubits heat up - Nature Electronics, Published online: 18 March 2022; doi:10.1038/s41928-022-00736-8 https://t.co/TpDZiVWvCH #semi https://t.co/8EFVKCIjsD



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[paper] Compound-Semiconductor Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli,
Richard Beanland, and Manus Hayne
ULTRARAM: A Low-Energy, High-Endurance, 
Compound-Semiconductor Memory on Silicon 
Adv. Electron. Mater. 2022, 2101103
DOI: 10.1002/aelm.202101103
  
Department of Physics, University of Warwick (UK)


Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.
Fig: ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/ erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

[paper] Electron Mobility Distribution in FD-SOI MOSFETs

Nima Dehdashti Akhavana, Gilberto Antonio Umana-Membrenoa, Renjie Gua, Jarek Antoszewskia, Lorenzo Faraonea and Sorin Cristoloveanub
Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach
Solid-State Electronics; Available online 14 March 2022, 108283
DOI: 10.1016/j.sse.2022.108283
   
a The University of Western Australia, Crawley (AU)
b IMEP-LAHC, INP Minatec, Grenoble (F)


Abstract: Modern electronic devices consist of several semiconductor layers, where each layer exhibits a unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Fig: Qinv is defined as the electron density per unit length at the maximum 
of the first subband (top of the barrier) often referred to as a “virtual source”

Acknowledgements: This work was supported by the Australian Research Council (DP170104555), the Horizon 2020 ASCENT EU project (Access to European Nanoelectronics Network – Project no. 654384), the Western Australian node of the Australian National Fabrication Facility (ANFF), and the Western Australian Government’s Department of Jobs, Tourism, Science and Innovation.