An indium oxide-based (#In2O3) #transistor created using atomic layer deposition

An indium oxide-based (#In2O3) #transistor created using atomic layer deposition https://t.co/zv8cpLNPIv #semi https://t.co/sxk3n5Dw0I

— Wladek Grabinski (@wladek60) Mar 17, 2022

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from Twitter https://twitter.com/wladek60

March 17, 2022 at 11:38PM
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This #Diamond #Transistor Is Still Raw, But Its Future Looks Bright

This #Diamond #Transistor Is Still Raw, But Its Future Looks Bright https://t.co/7NbI1TRClJ #semi https://t.co/WH7qrm8DtV

— Wladek Grabinski (@wladek60) Mar 17, 2022

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March 17, 2022 at 11:36PM
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Prof. Mathieu Luisier appointed as Full Professor of Computational Nanoelectronics at D-​ITET

Prof. Mathieu Luisier appointed as Full Professor of Computational Nanoelectronics at D-​ITET.

Congratulations!
#ethzurich #electricalengineering #professor #semi

https://t.co/KBIxHhb8rp

— Wladek Grabinski (@wladek60) Mar 17, 2022

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March 17, 2022 at 04:11PM
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Zero to ASIC Course https://t.co/65Dy5oHGPD #semi https://t.co/TnON0j7M8h

Zero to ASIC Course https://t.co/65Dy5oHGPD #semi https://t.co/TnON0j7M8h

— Wladek Grabinski (@wladek60) Mar 16, 2022

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from Twitter https://twitter.com/wladek60

March 16, 2022 at 05:06PM
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[paper] Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs

Sujit K. Singh, Sumreti Gupta, Reinaldo A. Vega* and Abhisek Dixit

Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3158495.

  

 Indian Institute of Technology, New Delhi (IN)

*IBM Research, Albany, NY (USA)

Abstract: In this letter, we have proposed modifications to the existing BSIM-CMG compact model to enhance its ability to model the behavior of short channel bulk FinFETs (both n and p-type) from room temperature down to cryogenic temperatures (10K). The proposed model is highly accurate in capturing the subthreshold swing, threshold voltage, and effective mobility trends observed in FinFET cryogenic operation. For efficient optimization of the proposed model parameters, we have proposed an adequate modeling strategy. We have compared convergence time between the existing BSIM-CMG model and the proposed model by simulating a reasonably large circuit using pseudo-inverters.

Fig (a) TEM image of the fin cross-section (b) Measured device layout-related parameters