[App Note] Frenetic use A.I. technology to design optimal transformers

Frenetic is a power electronics company created with the goal of making magnetics simple. Frenetic is revolutionizing the world of magnetics with A.I. technology, which is replacing the need for outdated engineering methods. The A.I. technology allows designing optimal transformers and inductors, build and test samples in our laboratory and get the best manufacturing solutions for our clients in order to ensure that quality and timelines are respected.

App Note: Planar Transformer with Half Turns

New proposed solution for the transformer was based on a 4-column structure, where the flux cancellations reduce the core losses and allow keeping high power density. The solution was used in an LLC converter, obtaining a power density of 55 W/cm3.

References
[1] Y. -C. Liu et al., "Design and Implementation of a Planar Transformer With Fractional Turns for High Power Density LLC Resonant Converters," in IEEE Transactions on Power Electronics, vol. 36, no. 5, pp. 5191-5203, May 2021, doi: 10.1109/TPEL.2020.3029001.
[2] D. Huang, S. Ji and F. C. Lee, "LLC resonant converter with matrix transformer", IEEE Trans. Power Electron., vol. 29, no. 8, pp. 4339-4347, Aug. 2014.
[3] C. Fei, F. C. Lee and Q. Li, "High-efficiency high-power-density LLC converter with an integrated planar matrix transformer for high-output current applications", IEEE Trans. Ind. Electron., vol. 64, no. 11, pp. 9072-9082, Nov. 2017.

[paper] Atomic-scale defects in Si/SiO2 transistors

Stephen J. Moxim1, Fedor V. Sharov1, David R. Hughart2, Gaddi S. Haase2, Colin G. McKay2, and Patrick M. Lenahan1

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO2 transistors

Appl. Phys. Lett. 120, 063502 (2022);

DOI:10.1063/5.0077946

   

1 The Pennsylvania State University, USA
2 Sandia National Laboratories, New Mexico, USA

Abstract: Electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO2 boundary. The interface traps observed are Pb0 and Pb1 centers, which are silicon dangling bond defects. The ratio of Pb0/Pb1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E′ oxide defects near the Si/SiO2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

FIG: Atomic-scale picture of defect formation and hydrogen motion during the early and intermediate stages of SiO2 degradation and breakdown.

Acknowledgements: This work was supported by the Defense Threat Reduction Agency (DTRA) under Award No. HDTRA1-18-0012. The content of the information does not necessarily reflect the position or the policy of the federal government and no official endorsement should be inferred

Aramco partners with Japan’s Yokogawa to localize chip manufacturing in Saudi Arabia

[https://t.co/AHsP5s1McG] Aramco partners with Japan’s Yokogawa to localize chip manufacturing in Saudi Arabia #semiconductorindustry #semi #semiconductor #manufacturing #Aramco #SaudiAramco #Yokogawa #HMLV #MANCEF #SEMI #SIA #IESA #IEEE #Semicon #chips…https://t.co/oQZRyJZbhV

— Wladek Grabinski (@wladek60) Feb 3, 2022

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from Twitter https://twitter.com/wladek60

February 03, 2022 at 05:35PM
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[ESSDERC/ESSCIRC 2022] Call for Papers

Paper submission is open!

Submission deadline: Apr 12, 2022 23:59 (GMT -0700)

Decision notification: May 31, 2022 23:59 (GMT -0700)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

PAPER SUBMISSION
Manuscript guidelines as well as instructions on how to submit electronically will be available on this website. Papers must not exceed four A4 pages with all illustrations and references included.

THE PAPERS SUBMISSION DEADLINE: APRIL 12, 2022

Papers submitted for review must clearly state:

•The purpose of the work

•How and to what extent it advances the state-of-the art

•Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 31 May 2022.

At the same time, the complete program will be published on the conference website. A binary feedback (accepted/rejected) with no comments will be provided to the authors. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

[paper] Transistor Modelling for mm-Wave Technology Pathfinding

B.Parvais1, R. ElKashlan1, H. Yu, A. Sibaja-Hernandez, B. Vermeersch, V. Putcha, P. Cardinael2, R. Rodriguez, A. Khaled, A. Alian, U. Peralagu, M. Zhao, S.Yadav, G. Gramegna, J. Van Driessche, N. Collaert

Transistor Modelling for mm-Wave Technology Pathfinding

SISPAD, 2021 

DOI: 10.1109/SISPAD54002.2021.959253

   
* imec, Kapeldreef 75, 3001 Leuven, Belgium
1 also with Vrije Universiteit Brussels, 1050 Brussels, Belgium
2 also with UCLouvain, Louvain-la-Neuve, Belgium

Abstract: A review of the modelling requirements to establish a Design-Technology Co-Optimization loop for mmWave Front-End Modules is presented. The example of GaN/Si technology is detailed, and recent modeling developments are explained.

Fig: The RF-DTCO loop concept: from device modeling

and exploration to benchmark circuits.