MPW-4 is open! Deadline is December 31, 2021

[https://t.co/H9QtSVW2z9] MPW-4 is open! Deadline is December 31, 2021. #Free fabrication for #opensource #chip projects. #semi #manufacturing #pdk #IC #SPICE https://t.co/zVCswKFbcL

— Wladek Grabinski (@wladek60) Nov 23, 2021

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from Twitter https://twitter.com/wladek60

November 23, 2021 at 05:25PM
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Samsung, 2nm will go into mass production in the 2nd Half of 2025

According to Samsung, 2nm will go into mass production in the 2nd Half of 2025 using a 3rd generation Gate-All-Around Field Effect Transistor Architecture (#GAA #FET) [https://t.co/gKjXIv5IPM] #GAAFET #Samsung #Foundry #semi #chips https://t.co/a8sUsp5KLm

— Wladek Grabinski (@wladek60) Nov 23, 2021

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from Twitter https://twitter.com/wladek60

November 23, 2021 at 05:28PM
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[paper] ACM Model for CMOS Analog Circuits Hand Design

Ademirde Jesus Costa^ab, Eliyas Mehdipour^b, Edson PintoSantana^b,

and Ana Isabela Araújo Cunha^b

Application of Improved ACM Model to the Design by Hand of CMOS Analog Circuits

Microelectronics Journal

Available online 16 November 2021, 105309

DOI: 10.1016/j.mejo.2021.105309

   
a Instituto Federal da Bahia, Santo Amaro, Brazil
b DEEC, Escola Politécnica, Universidade Federal da Bahia, Salvador, Brazil

Abstract: This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

Fig: gm/Id Plot

Nanorennes (CNRS)

 

Nanorennes was created in 2007 as a regional micro-technological platform, labelled by french national center of research and science (CNRS). This platform gathers on the same institute the know-how and human beings dedicated to the fabrication of nano-micrometer sized devices, related to two research laboratories located in Rennes : IETR-GM (microelectronic group) and FOTON-OHM (photonic group).

[paper] TFT XNOR/XOR Circuit

E. Bestelink, O. de Sagazan*, I. S. Pesch and R. A. Sporea

Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors

in IEEE TED, vol. 68, no. 10, pp. 4951-4955, Oct. 2021,

DOI: 10.1109/TED.2021.3103491.

  

Advanced Technology Institute, University of Surrey (UK)

* IETR-DMM-UMR6164, University of Rennes (F)

Abstract: A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

Fig: Micrograph of fabricated microcrystalline MMT devices and circuits. Inset: individual MMT devices with single device (MMT) and two source control gates (SUMFGMMT). Scale bars: 500μm.

Acknowledgement: Devices were fabricated on the NanoRennes platform.

CCBY - IEEE is not the copyright holder of this material.