[paper] 3nm Nano-Sheet FETs

Etienne SICARD* and Lionel TROJMAN**

Introducing 3-nm Nano-Sheet FET technology in Microwind

hal-03377556: Submitted on 14 Oct 2021

  

*INSA-Dgei, Toulouse (F)
**ISEP, Issy les Moulineaux (F)

Abstract: This paper describes the implementation of the novel Nano-sheet FET (NS-FET) for the 3-nm CMOS technology node in Microwind. After a general presentation of the electronic market and the roadmap to the atomic scale, design rules and basic metrics for the 3-nm node are presented. Concepts related to the design of NS-FET and design for manufacturing are also described. The performances of a ring oscillator, basic cells, sequential cells and a 6-transistor RAM memory are also analyzed.

Fig: A simple 3-stage ring oscillator based on compiled inverters “Fast” mode.

[ref] MICROWIND software allows the designer to simulate and design an integrated circuit at physical description level. Born in Toulouse (France), Microwind is an innovative CMOS design tool for educational market.

[TED paper] SPICE-Augmented ML to train machines to identify defects

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[paper] SET and CMOS circuits

Tetsufumi Tanamoto¹, and Keiji Ono²

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Appl. Phys. Lett. 119, 174002 (2021)

DOI: 10.1063/5.0068555

1Department of Information and Electronic Engineering, Teikyo University (J)
2Advanced Device Laboratory, RIKEN (J)

Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Fig: (a) Six transistor SRAM cells applied in the second-stage amplification 

(b) Time-dependent voltage behaviors of the SRAM setup of L = 90 nm  

(c) Replotting of (b) for L = 65 nm.

#Samsung to triple #foundry capacity

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#Apple joins as first public partner in new #imec research program

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